mirror of
https://github.com/physwizz/a155-U-u1.git
synced 2025-09-05 12:50:27 +00:00
398 lines
13 KiB
Plaintext
398 lines
13 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
|
/*
|
|
* Copyright (C) 2022 MediaTek Inc.
|
|
* Author: Owen Chen <owen.chen@mediatek.com>
|
|
*/
|
|
|
|
&disable_unused {
|
|
status = "okay";
|
|
disable-unused-clk-mdpsys {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&mdpsys_config_clk CLK_MDP_RDMA0>,
|
|
<&mdpsys_config_clk CLK_MDP_TDSHP0>,
|
|
<&mdpsys_config_clk CLK_MDP_IMG_DL_ASYNC0>,
|
|
<&mdpsys_config_clk CLK_MDP_IMG_DL_ASYNC1>,
|
|
<&mdpsys_config_clk CLK_MDP_SMI0>,
|
|
<&mdpsys_config_clk CLK_MDP_APB_BUS>,
|
|
<&mdpsys_config_clk CLK_MDP_WROT0>,
|
|
<&mdpsys_config_clk CLK_MDP_RSZ0>,
|
|
<&mdpsys_config_clk CLK_MDP_HDR0>,
|
|
<&mdpsys_config_clk CLK_MDP_MUTEX0>,
|
|
<&mdpsys_config_clk CLK_MDP_WROT1>,
|
|
<&mdpsys_config_clk CLK_MDP_RSZ1>,
|
|
<&mdpsys_config_clk CLK_MDP_FAKE_ENG0>,
|
|
<&mdpsys_config_clk CLK_MDP_AAL0>,
|
|
<&mdpsys_config_clk CLK_MDP_IMG_DL_RELAY0_ASYNC0>,
|
|
<&mdpsys_config_clk CLK_MDP_IMG_DL_RELAY1_ASYNC1>;
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_DISP>;
|
|
};
|
|
|
|
disable-unused-clk-ipesys {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&ipesys_clk CLK_IPE_LARB19>,
|
|
<&ipesys_clk CLK_IPE_LARB20>,
|
|
<&ipesys_clk CLK_IPE_SMI_SUBCOM>,
|
|
<&ipesys_clk CLK_IPE_FD>,
|
|
<&ipesys_clk CLK_IPE_FE>,
|
|
<&ipesys_clk CLK_IPE_RSC>,
|
|
<&ipesys_clk CLK_IPE_DPE>,
|
|
<&ipesys_clk CLK_IPE_GALS>;
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_IPE>;
|
|
};
|
|
|
|
disable-unused-clk-camsys_rawb {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&camsys_rawb_clk CLK_CAM_RB_LARBX>,
|
|
<&camsys_rawb_clk CLK_CAM_RB_CAM>,
|
|
<&camsys_rawb_clk CLK_CAM_RB_CAMTG>;
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_CAM_RAWB>;
|
|
};
|
|
|
|
disable-unused-clk-camsys_rawa {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&camsys_rawa_clk CLK_CAM_RA_LARBX>,
|
|
<&camsys_rawa_clk CLK_CAM_RA_CAM>,
|
|
<&camsys_rawa_clk CLK_CAM_RA_CAMTG>;
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_CAM_RAWA>;
|
|
};
|
|
|
|
disable-unused-clk-camsys_main {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&camsys_main_clk CLK_CAM_M_LARB13>,
|
|
<&camsys_main_clk CLK_CAM_M_LARB14>,
|
|
<&camsys_main_clk CLK_CAM_M_CAM>,
|
|
<&camsys_main_clk CLK_CAM_M_CAMTG>,
|
|
<&camsys_main_clk CLK_CAM_M_SENINF>,
|
|
<&camsys_main_clk CLK_CAM_M_CAMSV1>,
|
|
<&camsys_main_clk CLK_CAM_M_CAMSV2>,
|
|
<&camsys_main_clk CLK_CAM_M_CAMSV3>,
|
|
<&camsys_main_clk CLK_CAM_M_MRAW0>,
|
|
<&camsys_main_clk CLK_CAM_M_FAKE_ENG>,
|
|
<&camsys_main_clk CLK_CAM_M_CAM2MM_GALS>;
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_CAM>;
|
|
};
|
|
|
|
disable-unused-clk-vencsys {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&venc_gcon_clk CLK_VEN1_CKE0_LARB>,
|
|
<&venc_gcon_clk CLK_VEN1_CKE1_VENC>,
|
|
<&venc_gcon_clk CLK_VEN1_CKE2_JPGENC>,
|
|
<&venc_gcon_clk CLK_VEN1_CKE5_GALS>;
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_VENC>;
|
|
};
|
|
|
|
disable-unused-clk-vdecsys {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&vdec_gcon_base_clk CLK_VDE2_LARB1_CKEN>,
|
|
<&vdec_gcon_base_clk CLK_VDE2_LAT_CKEN>,
|
|
<&vdec_gcon_base_clk CLK_VDE2_LAT_ACTIVE>,
|
|
<&vdec_gcon_base_clk CLK_VDE2_LAT_CKEN_ENG>,
|
|
<&vdec_gcon_base_clk CLK_VDE2_MINI_MDP_CKEN_CFG_RG>,
|
|
<&vdec_gcon_base_clk CLK_VDE2_VDEC_CKEN>,
|
|
<&vdec_gcon_base_clk CLK_VDE2_VDEC_ACTIVE>,
|
|
<&vdec_gcon_base_clk CLK_VDE2_VDEC_CKEN_ENG>;
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_VDEC>;
|
|
};
|
|
|
|
disable-unused-clk-imgsys1 {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&imgsys1_clk CLK_IMGSYS1_LARB9>,
|
|
<&imgsys1_clk CLK_IMGSYS1_LARB10>,
|
|
<&imgsys1_clk CLK_IMGSYS1_DIP>,
|
|
<&imgsys1_clk CLK_IMGSYS1_GALS>;
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_ISP>;
|
|
};
|
|
|
|
disable-unused-clk-mmsys {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&dispsys_config_clk CLK_MM_DISP_MUTEX0>,
|
|
<&dispsys_config_clk CLK_MM_APB_BUS>,
|
|
<&dispsys_config_clk CLK_MM_DISP_OVL0>,
|
|
<&dispsys_config_clk CLK_MM_DISP_RDMA0>,
|
|
<&dispsys_config_clk CLK_MM_DISP_OVL0_2L>,
|
|
<&dispsys_config_clk CLK_MM_DISP_WDMA0>,
|
|
<&dispsys_config_clk CLK_MM_DISP_RSZ0>,
|
|
<&dispsys_config_clk CLK_MM_DISP_AAL0>,
|
|
<&dispsys_config_clk CLK_MM_DISP_CCORR0>,
|
|
<&dispsys_config_clk CLK_MM_DISP_COLOR0>,
|
|
<&dispsys_config_clk CLK_MM_SMI_INFRA>,
|
|
<&dispsys_config_clk CLK_MM_DISP_DSC_WRAP0>,
|
|
<&dispsys_config_clk CLK_MM_DISP_GAMMA0>,
|
|
<&dispsys_config_clk CLK_MM_DISP_POSTMASK0>,
|
|
<&dispsys_config_clk CLK_MM_DISP_DITHER0>,
|
|
<&dispsys_config_clk CLK_MM_SMI_COMMON>,
|
|
<&dispsys_config_clk CLK_MM_DSI0>,
|
|
<&dispsys_config_clk CLK_MM_DISP_FAKE_ENG0>,
|
|
<&dispsys_config_clk CLK_MM_DISP_FAKE_ENG1>,
|
|
<&dispsys_config_clk CLK_MM_SMI_GALS>,
|
|
<&dispsys_config_clk CLK_MM_SMI_IOMMU>,
|
|
<&dispsys_config_clk CLK_MM_DSI0_DSI_CK_DOMAIN>,
|
|
<&dispsys_config_clk CLK_MM_DISP_26M>;
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_DISP>;
|
|
};
|
|
|
|
disable-unused-clk-imp_iic_wrap_n {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&imp_iic_wrap_n_clk CLK_IMPN_AP_CLOCK_I2C7>;
|
|
};
|
|
|
|
disable-unused-clk-imp_iic_wrap_en {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&imp_iic_wrap_en_clk CLK_IMPEN_AP_CLOCK_I2C2>,
|
|
<&imp_iic_wrap_en_clk CLK_IMPEN_AP_CLOCK_I2C4>,
|
|
<&imp_iic_wrap_en_clk CLK_IMPEN_AP_CLOCK_I2C8>,
|
|
<&imp_iic_wrap_en_clk CLK_IMPEN_AP_CLOCK_I2C9>;
|
|
};
|
|
|
|
disable-unused-clk-imp_iic_wrap_w {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&imp_iic_wrap_w_clk CLK_IMPW_AP_CLOCK_I2C0>,
|
|
<&imp_iic_wrap_w_clk CLK_IMPW_AP_CLOCK_I2C1>;
|
|
};
|
|
|
|
disable-unused-clk-afe {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&afe_clk CLK_AFE_AFE>,
|
|
<&afe_clk CLK_AFE_22M>,
|
|
<&afe_clk CLK_AFE_24M>,
|
|
<&afe_clk CLK_AFE_APLL2_TUNER>,
|
|
<&afe_clk CLK_AFE_APLL_TUNER>,
|
|
<&afe_clk CLK_AFE_ADC>,
|
|
<&afe_clk CLK_AFE_DAC>,
|
|
<&afe_clk CLK_AFE_DAC_PREDIS>,
|
|
<&afe_clk CLK_AFE_TML>,
|
|
<&afe_clk CLK_AFE_NLE>,
|
|
<&afe_clk CLK_AFE_I2S1_BCLK>,
|
|
<&afe_clk CLK_AFE_I2S2_BCLK>,
|
|
<&afe_clk CLK_AFE_I2S3_BCLK>,
|
|
<&afe_clk CLK_AFE_I2S4_BCLK>,
|
|
<&afe_clk CLK_AFE_GENERAL3_ASRC>,
|
|
<&afe_clk CLK_AFE_CONNSYS_I2S_ASRC>,
|
|
<&afe_clk CLK_AFE_GENERAL1_ASRC>,
|
|
<&afe_clk CLK_AFE_GENERAL2_ASRC>,
|
|
<&afe_clk CLK_AFE_DAC_HIRES>,
|
|
<&afe_clk CLK_AFE_ADC_HIRES>,
|
|
<&afe_clk CLK_AFE_ADC_HIRES_TML>;
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_AUDIO>;
|
|
};
|
|
|
|
disable-unused-clk-imp_iic_wrap_c {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&imp_iic_wrap_c_clk CLK_IMPC_AP_CLOCK_I2C3>,
|
|
<&imp_iic_wrap_c_clk CLK_IMPC_AP_CLOCK_I2C5>,
|
|
<&imp_iic_wrap_c_clk CLK_IMPC_AP_CLOCK_I2C6>;
|
|
};
|
|
|
|
disable-unused-clk-infracfg_ao {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&infracfg_ao_clk CLK_IFRAO_PMIC_TMR>,
|
|
<&infracfg_ao_clk CLK_IFRAO_PMIC_AP>,
|
|
<&infracfg_ao_clk CLK_IFRAO_GCE>,
|
|
<&infracfg_ao_clk CLK_IFRAO_GCE2>,
|
|
<&infracfg_ao_clk CLK_IFRAO_THERM>,
|
|
<&infracfg_ao_clk CLK_IFRAO_I2C_PSEUDO>,
|
|
<&infracfg_ao_clk CLK_IFRAO_APDMA_PSEUDO>,
|
|
<&infracfg_ao_clk CLK_IFRAO_PWM_HCLK>,
|
|
<&infracfg_ao_clk CLK_IFRAO_PWM1>,
|
|
<&infracfg_ao_clk CLK_IFRAO_PWM2>,
|
|
<&infracfg_ao_clk CLK_IFRAO_PWM3>,
|
|
<&infracfg_ao_clk CLK_IFRAO_PWM4>,
|
|
<&infracfg_ao_clk CLK_IFRAO_PWM>,
|
|
<&infracfg_ao_clk CLK_IFRAO_UART0>,
|
|
<&infracfg_ao_clk CLK_IFRAO_UART1>,
|
|
<&infracfg_ao_clk CLK_IFRAO_UART2>,
|
|
<&infracfg_ao_clk CLK_IFRAO_UART3>,
|
|
<&infracfg_ao_clk CLK_IFRAO_GCE_26M>,
|
|
<&infracfg_ao_clk CLK_IFRAO_BTIF>,
|
|
<&infracfg_ao_clk CLK_IFRAO_SPI0>,
|
|
<&infracfg_ao_clk CLK_IFRAO_MSDC0>,
|
|
<&infracfg_ao_clk CLK_IFRAO_MSDC1>,
|
|
<&infracfg_ao_clk CLK_IFRAO_MSDC0_SRC>,
|
|
<&infracfg_ao_clk CLK_IFRAO_AUXADC>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CPUM>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF1_AP>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF1_MD>,
|
|
<&infracfg_ao_clk CLK_IFRAO_AUXADC_MD>,
|
|
<&infracfg_ao_clk CLK_IFRAO_MSDC1_SRC>,
|
|
<&infracfg_ao_clk CLK_IFRAO_MSDC0_AES>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF_AP>,
|
|
<&infracfg_ao_clk CLK_IFRAO_DEBUGSYS>,
|
|
<&infracfg_ao_clk CLK_IFRAO_AUDIO>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF_MD>,
|
|
<&infracfg_ao_clk CLK_IFRAO_SSUSB>,
|
|
<&infracfg_ao_clk CLK_IFRAO_DISP_PWM>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CLDMA_BCLK>,
|
|
<&infracfg_ao_clk CLK_IFRAO_AUDIO_26M_BCLK>,
|
|
<&infracfg_ao_clk CLK_IFRAO_SPI1>,
|
|
<&infracfg_ao_clk CLK_IFRAO_SPI2>,
|
|
<&infracfg_ao_clk CLK_IFRAO_SPI3>,
|
|
<&infracfg_ao_clk CLK_IFRAO_UNIPRO_SYSCLK>,
|
|
<&infracfg_ao_clk CLK_IFRAO_UNIPRO_TICK>,
|
|
<&infracfg_ao_clk CLK_IFRAO_UFS_SAP_BCLK>,
|
|
<&infracfg_ao_clk CLK_IFRAO_SPI4>,
|
|
<&infracfg_ao_clk CLK_IFRAO_SPI5>,
|
|
<&infracfg_ao_clk CLK_IFRAO_UFS>,
|
|
<&infracfg_ao_clk CLK_IFRAO_UFS_AES>,
|
|
<&infracfg_ao_clk CLK_IFRAO_AP_MSDC0>,
|
|
<&infracfg_ao_clk CLK_IFRAO_MD_MSDC0>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF5_MD>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF2_AP>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF2_MD>,
|
|
<&infracfg_ao_clk CLK_IFRAO_FBIST2FPC>,
|
|
<&infracfg_ao_clk CLK_IFRAO_DPMAIF_MAIN>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF4_AP>,
|
|
<&infracfg_ao_clk CLK_IFRAO_CCIF4_MD>,
|
|
<&infracfg_ao_clk CLK_IFRAO_SPI6_CK>,
|
|
<&infracfg_ao_clk CLK_IFRAO_SPI7_CK>,
|
|
<&infracfg_ao_clk CLK_IFRAO_66MP_BUS_MCLK_CKP>,
|
|
<&infracfg_ao_clk CLK_IFRAO_AP_DMA>;
|
|
};
|
|
|
|
disable-unused-clk-topckgen {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV0>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV1>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV2>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV3>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV4>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIVB>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV5>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV6>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV7>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV8>,
|
|
<&topckgen_clk CLK_TOP_APLL12_CK_DIV9>,
|
|
<&topckgen_clk CLK_TOP_SCP_SEL>,
|
|
<&topckgen_clk CLK_TOP_DISP_SEL>,
|
|
<&topckgen_clk CLK_TOP_MDP_SEL>,
|
|
<&topckgen_clk CLK_TOP_IMG1_SEL>,
|
|
<&topckgen_clk CLK_TOP_IPE_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAM_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG2_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG3_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG4_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG5_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTG6_SEL>,
|
|
<&topckgen_clk CLK_TOP_UART_SEL>,
|
|
<&topckgen_clk CLK_TOP_SPI_SEL>,
|
|
<&topckgen_clk CLK_TOP_MSDC50_0_HCLK_SEL>,
|
|
<&topckgen_clk CLK_TOP_MSDC50_0_SEL>,
|
|
<&topckgen_clk CLK_TOP_MSDC30_1_SEL>,
|
|
<&topckgen_clk CLK_TOP_AUDIO_SEL>,
|
|
<&topckgen_clk CLK_TOP_AUD_INTBUS_SEL>,
|
|
<&topckgen_clk CLK_TOP_PWRAP_ULPOSC_SEL>,
|
|
<&topckgen_clk CLK_TOP_ATB_SEL>,
|
|
<&topckgen_clk CLK_TOP_SCAM_SEL>,
|
|
<&topckgen_clk CLK_TOP_DISP_PWM_SEL>,
|
|
<&topckgen_clk CLK_TOP_USB_TOP_SEL>,
|
|
<&topckgen_clk CLK_TOP_I2C_SEL>,
|
|
<&topckgen_clk CLK_TOP_SENINF_SEL>,
|
|
<&topckgen_clk CLK_TOP_SENINF1_SEL>,
|
|
<&topckgen_clk CLK_TOP_SENINF2_SEL>,
|
|
<&topckgen_clk CLK_TOP_SENINF3_SEL>,
|
|
<&topckgen_clk CLK_TOP_AUD_ENGEN1_SEL>,
|
|
<&topckgen_clk CLK_TOP_AUD_ENGEN2_SEL>,
|
|
<&topckgen_clk CLK_TOP_AES_UFSFDE_SEL>,
|
|
<&topckgen_clk CLK_TOP_UFS_SEL>,
|
|
<&topckgen_clk CLK_TOP_AUD_1_SEL>,
|
|
<&topckgen_clk CLK_TOP_AUD_2_SEL>,
|
|
<&topckgen_clk CLK_TOP_DPMAIF_MAIN_SEL>,
|
|
<&topckgen_clk CLK_TOP_VENC_SEL>,
|
|
<&topckgen_clk CLK_TOP_VDEC_SEL>,
|
|
<&topckgen_clk CLK_TOP_CAMTM_SEL>,
|
|
<&topckgen_clk CLK_TOP_PWM_SEL>,
|
|
<&topckgen_clk CLK_TOP_AUDIO_H_SEL>,
|
|
<&topckgen_clk CLK_TOP_AES_MSDCFDE_SEL>,
|
|
<&topckgen_clk CLK_TOP_DSI_OCC_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S0_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S1_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S2_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S3_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S4_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S5_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S6_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S7_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S8_MCK_SEL>,
|
|
<&topckgen_clk CLK_TOP_APLL_I2S9_MCK_SEL>;
|
|
};
|
|
|
|
disable-unused-clk-apmixedsys {
|
|
compatible = "mediatek,clk-disable-unused";
|
|
clocks =
|
|
<&apmixedsys_clk CLK_APMIXED_ARMPLL_LL>,
|
|
<&apmixedsys_clk CLK_APMIXED_ARMPLL_BL0>,
|
|
<&apmixedsys_clk CLK_APMIXED_CCIPLL>,
|
|
<&apmixedsys_clk CLK_APMIXED_MPLL>,
|
|
<&apmixedsys_clk CLK_APMIXED_MAINPLL>,
|
|
<&apmixedsys_clk CLK_APMIXED_UNIVPLL>,
|
|
<&apmixedsys_clk CLK_APMIXED_MSDCPLL>,
|
|
<&apmixedsys_clk CLK_APMIXED_MMPLL>,
|
|
<&apmixedsys_clk CLK_APMIXED_NPUPLL>,
|
|
<&apmixedsys_clk CLK_APMIXED_TVDPLL>,
|
|
<&apmixedsys_clk CLK_APMIXED_APLL1>,
|
|
<&apmixedsys_clk CLK_APMIXED_APLL2>,
|
|
<&apmixedsys_clk CLK_APMIXED_USBPLL>;
|
|
};
|
|
|
|
disable-unused-pd-isp {
|
|
compatible = "mediatek,scpsys-disable-unused";
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_ISP>;
|
|
};
|
|
|
|
disable-unused-pd-ipe {
|
|
compatible = "mediatek,scpsys-disable-unused";
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_IPE>;
|
|
};
|
|
|
|
disable-unused-pd-vdec {
|
|
compatible = "mediatek,scpsys-disable-unused";
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_VDEC>;
|
|
};
|
|
|
|
disable-unused-pd-venc {
|
|
compatible = "mediatek,scpsys-disable-unused";
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_VENC>;
|
|
};
|
|
|
|
disable-unused-pd-disp {
|
|
compatible = "mediatek,scpsys-disable-unused";
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_DISP>;
|
|
};
|
|
|
|
disable-unused-pd-audio {
|
|
compatible = "mediatek,scpsys-disable-unused";
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_AUDIO>;
|
|
};
|
|
|
|
disable-unused-pd-cam {
|
|
compatible = "mediatek,scpsys-disable-unused";
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_CAM>;
|
|
};
|
|
|
|
disable-unused-pd-cam_rawa {
|
|
compatible = "mediatek,scpsys-disable-unused";
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_CAM_RAWA>;
|
|
};
|
|
|
|
disable-unused-pd-cam_rawb {
|
|
compatible = "mediatek,scpsys-disable-unused";
|
|
power-domains = <&scpsys MT6789_POWER_DOMAIN_CAM_RAWB>;
|
|
};
|
|
};
|