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70 lines
2.5 KiB
Diff
70 lines
2.5 KiB
Diff
From 0845d9b5935ad8b3d450c2dfa62631c9c1df1bea Mon Sep 17 00:00:00 2001
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From: Khem Raj <raj.khem@gmail.com>
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Date: Tue, 7 Mar 2023 21:21:57 -0800
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Subject: [PATCH 4/4] PCI: imx: Provide a clock to the device for i.MX8MQ
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When the internal PLL is configured as PCIe REF_CLK, we also have to
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output a clock via CLK2_P/N pin to the connector/device to provide it.
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Configure 100 MHz clock as its output.
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Signed-off-by: Ryosuke Saito <rsaito@redhat.com>
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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---
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drivers/pci/controller/dwc/pci-imx6.c | 35 +++++++++++++++++++++++++++
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1 file changed, 35 insertions(+)
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diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
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index 841af6f55c7d..ac36c7035460 100644
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--- a/drivers/pci/controller/dwc/pci-imx6.c
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+++ b/drivers/pci/controller/dwc/pci-imx6.c
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@@ -43,6 +43,11 @@ struct imx6_pcie {
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#define IMX8MQ_GPR_PCIE_VREG_BYPASS BIT(12)
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#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE GENMASK(11, 8)
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#define IMX8MQ_PCIE2_BASE_ADDR 0x33c00000
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+#define IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG 0x74
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+#define IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK GENMASK(3, 0)
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+#define IMX8MQ_ANA_PLLOUT_MONITOR_CKE BIT(4)
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+#define IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG 0x7C
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+#define IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK GENMASK(2, 0)
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#define IMX95_PCIE_PHY_GEN_CTRL 0x0
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#define IMX95_PCIE_REF_USE_PAD BIT(17)
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@@ -370,6 +370,34 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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imx_pcie_grp_offset(imx_pcie),
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IMX8MQ_GPR_PCIE_REF_USE_PAD,
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IMX8MQ_GPR_PCIE_REF_USE_PAD);
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+ } else {
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+ /*
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+ * Use the internal PLL as REF clock and also
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+ * provide a clock to the device.
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+ */
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+ struct regmap *anatop =
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+ syscon_regmap_lookup_by_compatible("fsl,imx8mq-anatop");
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+
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+ if (IS_ERR(anatop)) {
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+ dev_err(imx_pcie->pci->dev,
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+ "Couldn't configure the internal PLL as REF clock\n");
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+ } else {
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+ /* Select SYSTEM_PLL1_CLK as the clock source */
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+ regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG,
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+ IMX8MQ_ANA_PLLOUT_MONITOR_CLK_SEL_MASK, 0xb);
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+
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+ /*
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+ * SYSTEM_PLL1_CLK is 800 MHz, so divided by 8
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+ * for generating 100 MHz as output.
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+ */
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+ regmap_update_bits(anatop, IMX8MQ_ANA_SCCG_PLLOUT_DIV_CFG_REG,
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+ IMX8MQ_ANA_SCCG_SYSPLLL1_DIV_MASK, 0x7);
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+
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+ /* Enable CLK2_P/N clock to provide it to the device */
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+ regmap_update_bits(anatop, IMX8MQ_ANA_PLLOUT_MONITOR_CFG_REG,
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+ IMX8MQ_ANA_PLLOUT_MONITOR_CKE,
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+ IMX8MQ_ANA_PLLOUT_MONITOR_CKE);
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+ }
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}
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/*
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* Regarding the datasheet, the PCIE_VPH is suggested to be 1.8V. If the PCIE_VPH is
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--
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2.39.2
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