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58 lines
2.0 KiB
Diff
58 lines
2.0 KiB
Diff
From f248ceae106d48ff1b1a81a32fdd5d0f4ad9c40e Mon Sep 17 00:00:00 2001
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From: Jerome Brunet <jbrunet@baylibre.com>
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Date: Fri, 20 Dec 2024 11:25:37 +0100
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Subject: [PATCH 15/58] FROMGIT(6.14): clk: amlogic: gxbb: drop non existing
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32k clock parent
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The 32k clock reference a parent 'cts_slow_oscin' with a fixme note saying
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that this clock should be provided by AO controller.
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The HW probably has this clock but it does not exist at the moment in
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any controller implementation. Furthermore, referencing clock by the global
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name should be avoided whenever possible.
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There is no reason to keep this hack around, at least for now.
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Fixes: 14c735c8e308 ("clk: meson-gxbb: Add EE 32K Clock for CEC")
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Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
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Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
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---
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drivers/clk/meson/gxbb.c | 12 ++++++------
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1 file changed, 6 insertions(+), 6 deletions(-)
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diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
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index 738317b3e274..d9529de200ae 100644
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--- a/drivers/clk/meson/gxbb.c
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+++ b/drivers/clk/meson/gxbb.c
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@@ -1272,14 +1272,13 @@ static struct clk_regmap gxbb_cts_i958 = {
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},
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};
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+/*
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+ * This table skips a clock named 'cts_slow_oscin' in the documentation
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+ * This clock does not exist yet in this controller or the AO one
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+ */
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+static u32 gxbb_32k_clk_parents_val_table[] = { 0, 2, 3 };
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static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
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{ .fw_name = "xtal", },
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- /*
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- * FIXME: This clock is provided by the ao clock controller but the
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- * clock is not yet part of the binding of this controller, so string
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- * name must be use to set this parent.
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- */
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- { .name = "cts_slow_oscin", .index = -1 },
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{ .hw = &gxbb_fclk_div3.hw },
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{ .hw = &gxbb_fclk_div5.hw },
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};
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@@ -1289,6 +1288,7 @@ static struct clk_regmap gxbb_32k_clk_sel = {
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.offset = HHI_32K_CLK_CNTL,
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.mask = 0x3,
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.shift = 16,
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+ .table = gxbb_32k_clk_parents_val_table,
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},
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.hw.init = &(struct clk_init_data){
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.name = "32k_clk_sel",
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--
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2.34.1
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