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600e246a94
Lakka 5.x Switch changes (#1853) Lakka v5.x switchroot 5.1.2 (#1871) Fix Switch Issue's in upstream 5.x (#1888) Minor Switch Changes (#1893) Lakka v5.x switch 3 (#1895) Lakka v5.x switch 4 (#1898) L4T: Xorg-server: Fix build issue (#1924) Switch: remove ra patch Lakka v5.x switch 6 (#1926) Cleanups, More LibreELEC Stuff, more permission fixes, Misc switch stuff. (#1930) Switch: U-Boot: bump version to 2024-NX02 (#1946) L4T/Ayn post-upstreaming fixes - retroarch_joypad_autoconfig: remove spaces from file names - retroarch: remove Switch specific patch merged upstream - libXv: move to L4T packages folder (package removed in upstream) - bring some packages from v5.x to L4T packages - ffmpeg: remove vulkan - remove stella core from Switch build (missing C++ headers) - Ayn/Odin: use proper kernel arg to not hide kernel messages in console - connman: add wpa_supplicant support back
84 lines
3.1 KiB
Diff
84 lines
3.1 KiB
Diff
From c5751e2bb1faeb0fd8e4442461bbbcd9448c3960 Mon Sep 17 00:00:00 2001
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From: CTCaer <ctcaer@gmail.com>
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Date: Wed, 29 Jun 2022 06:38:26 +0000
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Subject: [PATCH 19/39] codecs: nvv4l2: align enc plane width per format/plane
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Take two on creating a heuristic of the needed alignment.
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Unlike in VIC/NVDEC, in encoding the conversion is from Pitch to Block linear.
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That needs precise alignments for each plane, per format.
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This supports way more resolutions than before, but still lacks support for non-standard ones.
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For example, 854 width needs 32B alignment (instead of 64!) for yuv420 on main plane.
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And the other 2 planes need 64B.
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As usual, TRM is not helpful on that (only has 64/256B alignments for block/pitch)
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and there's probably an algorithm on the drivers that causes that issue by aligning
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sizes for NVENC without notifying user.
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---
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libavcodec/nvv4l2_enc.c | 38 ++++++++++++++++++++++++++++++++------
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1 file changed, 32 insertions(+), 6 deletions(-)
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diff --git a/libavcodec/nvv4l2_enc.c b/libavcodec/nvv4l2_enc.c
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index 7bd8e84227..6fc74472ef 100644
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--- a/libavcodec/nvv4l2_enc.c
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+++ b/libavcodec/nvv4l2_enc.c
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@@ -646,6 +646,7 @@ int nvv4l2_encoder_put_frame(AVCodecContext *avctx, nvv4l2_ctx_t *ctx,
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NvFrame *frame)
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{
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int ret;
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+ int alignment;
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struct v4l2_buffer v4l2_buf_op;
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struct v4l2_plane queue_op_planes[NV_MAX_PLANES];
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NvBuffer *buffer;
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@@ -685,14 +686,39 @@ int nvv4l2_encoder_put_frame(AVCodecContext *avctx, nvv4l2_ctx_t *ctx,
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}
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}
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+ /*
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+ ** Due to NvMap/VIC stride conversion constrains, the transformation
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+ ** must be aligned per format/plane. Otherwise the frame might be
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+ ** produced as scrambled.
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+ **
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+ ** !TODO: Have a proper algorithm to calculate needed alignements.
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+ */
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+ switch (ctx->op_pixfmt) {
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+ case V4L2_PIX_FMT_NV12M:
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+ alignment = 16;
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+ break;
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+ case V4L2_PIX_FMT_YUV420M:
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+ alignment = 64;
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+ break;
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+ case V4L2_PIX_FMT_YUV444M:
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+ alignment = 32;
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+ break;
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+ case V4L2_PIX_FMT_P010M:
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+ default:
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+ alignment = 1;
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+ break;
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+ }
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+
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/* Import frame into output plane */
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for (uint32_t i = 0; i < buffer->n_planes; i++) {
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- /*
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- ** Due to VIC constrains the transformation from Block Linear to Pitch
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- ** must have aligned widths to 64B. Otherwise the frame might be
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- ** produced as scrambled.
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- */
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- int aligned_plane_width = NVALIGN(ctx->op_planefmts[i].width, 64);
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+ int aligned_plane_width = NVALIGN(ctx->op_planefmts[i].width, alignment);
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+
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+ /* If plane is reduced, use alignment of main plane */
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+ if (ctx->op_planefmts[i].width == ctx->op_planefmts[0].width / 2)
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+ aligned_plane_width = NVALIGN(ctx->op_planefmts[0].width, alignment) / 2;
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+
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+ av_log(avctx, AV_LOG_VERBOSE, "Plane %d: width %d -> %d\n",
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+ i, ctx->op_planefmts[i].width, aligned_plane_width);
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Raw2NvBuffer(frame->payload[i], i, aligned_plane_width,
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ctx->op_planefmts[i].height, buffer->planes[i].fd);
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--
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2.25.1
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