mirror of
https://github.com/libretro/Lakka-LibreELEC.git
synced 2024-12-15 19:09:46 +00:00
cfc938c153
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
110 lines
4.1 KiB
Diff
110 lines
4.1 KiB
Diff
From 7354c155f1956487683a192e629cda68bcd38bd8 Mon Sep 17 00:00:00 2001
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From: Christian Hewitt <christianshewitt@gmail.com>
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Date: Tue, 18 Jan 2022 15:09:12 +0000
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Subject: [PATCH 43/53] WIP: arm64: dts: meson: set p212/p23x/q20x SDIO to
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100MHz
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Amlogic datasheets describe 50MHz max-frequency for SDIO on GXL/GXM but
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real-world tests on an assortment of GXL and GXM boards show noteable
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increases in throughput when max-frequency is 100MHz, so let's use it.
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Before results from a p231 device:
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Connecting to host 192.168.0.1, port 5201
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Reverse mode, remote host 192.168.0.1 is sending
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[ 5] local 192.168.0.41 port 42550 connected to 192.168.0.1 port 5201
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[ ID] Interval Transfer Bitrate
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[ 5] 0.00-1.00 sec 8.84 MBytes 74.2 Mbits/sec
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[ 5] 1.00-2.00 sec 9.60 MBytes 80.5 Mbits/sec
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[ 5] 2.00-3.00 sec 9.07 MBytes 76.1 Mbits/sec
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[ 5] 3.00-4.00 sec 9.14 MBytes 76.6 Mbits/sec
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[ 5] 4.00-5.00 sec 9.26 MBytes 77.7 Mbits/sec
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[ 5] 5.00-6.00 sec 9.08 MBytes 76.2 Mbits/sec
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[ 5] 6.00-7.00 sec 9.11 MBytes 76.4 Mbits/sec
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[ 5] 7.00-8.00 sec 8.65 MBytes 72.5 Mbits/sec
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[ 5] 8.00-9.00 sec 9.24 MBytes 77.5 Mbits/sec
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[ 5] 9.00-10.00 sec 8.57 MBytes 71.9 Mbits/sec
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- - - - - - - - - - - - - - - - - - - - - - - - -
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[ ID] Interval Transfer Bitrate Retr
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[ 5] 0.00-10.27 sec 94.1 MBytes 76.8 Mbits/sec 0 sender
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[ 5] 0.00-10.00 sec 90.6 MBytes 76.0 Mbits/sec receiver
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clock: 50000000 Hz
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actual clock: 50000000 Hz
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vdd: 21 (3.3 ~ 3.4 V)
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bus mode: 2 (push-pull)
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chip select: 0 (don't care)
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power mode: 2 (on)
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bus width: 2 (4 bits)
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timing spec: 2 (sd high-speed)
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signal voltage: 1 (1.80 V)
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driver type: 0 (driver type B)
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After results from a p231 device:
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Connecting to host 192.168.0.1, port 5201
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Reverse mode, remote host 192.168.0.1 is sending
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[ 5] local 192.168.0.41 port 58534 connected to 192.168.0.1 port 5201
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[ ID] Interval Transfer Bitrate
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[ 5] 0.00-1.00 sec 12.6 MBytes 106 Mbits/sec
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[ 5] 1.00-2.00 sec 13.0 MBytes 109 Mbits/sec
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[ 5] 2.00-3.00 sec 12.8 MBytes 107 Mbits/sec
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[ 5] 3.00-4.00 sec 13.2 MBytes 111 Mbits/sec
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[ 5] 4.00-5.00 sec 12.4 MBytes 104 Mbits/sec
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[ 5] 5.00-6.00 sec 11.2 MBytes 93.9 Mbits/sec
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[ 5] 6.00-7.00 sec 12.3 MBytes 103 Mbits/sec
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[ 5] 7.00-8.00 sec 12.3 MBytes 103 Mbits/sec
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[ 5] 8.00-9.00 sec 12.5 MBytes 105 Mbits/sec
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[ 5] 9.00-10.00 sec 12.3 MBytes 103 Mbits/sec
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- - - - - - - - - - - - - - - - - - - - - - - - -
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[ ID] Interval Transfer Bitrate Retr
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[ 5] 0.00-10.22 sec 127 MBytes 104 Mbits/sec 0 sender
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[ 5] 0.00-10.00 sec 125 MBytes 105 Mbits/sec receiver
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clock: 100000000 Hz
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actual clock: 100000000 Hz
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vdd: 21 (3.3 ~ 3.4 V)
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bus mode: 2 (push-pull)
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chip select: 0 (don't care)
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power mode: 2 (on)
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bus width: 2 (4 bits)
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timing spec: 6 (sd uhs SDR104)
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signal voltage: 1 (1.80 V)
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driver type: 0 (driver type B)
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Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
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---
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arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 2 +-
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arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi | 2 +-
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2 files changed, 2 insertions(+), 2 deletions(-)
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diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
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index 08d6b69ba469..9ac5079019fa 100644
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--- a/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
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+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
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@@ -256,7 +256,7 @@ &sd_emmc_a {
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bus-width = <4>;
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cap-sd-highspeed;
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- max-frequency = <50000000>;
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+ max-frequency = <100000000>;
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non-removable;
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disable-wp;
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diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
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index 7e7dc87ede2d..1c64b2d64ae8 100644
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--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
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+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi
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@@ -121,7 +121,7 @@ &sd_emmc_a {
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bus-width = <4>;
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cap-sd-highspeed;
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- max-frequency = <50000000>;
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+ max-frequency = <100000000>;
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non-removable;
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disable-wp;
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--
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2.34.1
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