mirror of
https://github.com/libretro/Lakka-LibreELEC.git
synced 2024-12-15 19:09:46 +00:00
454 lines
12 KiB
Diff
454 lines
12 KiB
Diff
From d7b2340cd84ba5ce3494e8acbf52191e1d85bbe8 Mon Sep 17 00:00:00 2001
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From: Jernej Skrabec <jernej.skrabec@siol.net>
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Date: Wed, 20 Jan 2021 22:15:36 +0100
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Subject: [PATCH 22/23] wip h3/h5 cvbs
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---
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arch/arm/boot/dts/allwinner/sun8i-h3.dtsi | 22 +++++
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arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi | 95 +++++++++++++++++++-
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arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 22 +++++
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drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 14 ++-
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drivers/gpu/drm/sun4i/sun4i_tv.c | 35 +++++++-
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drivers/gpu/drm/sun4i/sun8i_mixer.c | 38 ++++++++
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drivers/gpu/drm/sun4i/sun8i_mixer.h | 5 +-
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7 files changed, 223 insertions(+), 8 deletions(-)
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diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
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index eac2349a2380..411640fca509 100644
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--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
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+++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
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@@ -239,6 +239,20 @@ ths: thermal-sensor@1c25000 {
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nvmem-cell-names = "calibration";
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#thermal-sensor-cells = <0>;
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};
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+
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+ tve: tv-encoder@1e00000 {
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+ compatible = "allwinner,sun8i-h3-tv-encoder";
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+ reg = <0x01e00000 0x1000>;
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+ clocks = <&ccu CLK_BUS_TVE>;
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+ resets = <&ccu RST_BUS_TVE>;
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+ status = "disabled";
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+
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+ port {
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+ tve_in_tcon1: endpoint {
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+ remote-endpoint = <&tcon1_out_tve>;
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+ };
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+ };
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+ };
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};
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thermal-zones {
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@@ -286,6 +300,10 @@ &mbus {
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compatible = "allwinner,sun8i-h3-mbus";
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};
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+&mixer1 {
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+ resets = <&display_clocks RST_WB>;
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+};
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+
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&mmc0 {
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compatible = "allwinner,sun7i-a20-mmc";
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clocks = <&ccu CLK_BUS_MMC0>,
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@@ -333,3 +351,7 @@ &rtc {
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&sid {
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compatible = "allwinner,sun8i-h3-sid";
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};
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+
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+&tcon1_out_tve {
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+ remote-endpoint = <&tve_in_tcon1>;
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+};
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diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
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index ade1cd50e445..dc2ae4270347 100644
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--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
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+++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
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@@ -102,7 +102,7 @@ osc32k: osc32k_clk {
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de: display-engine {
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compatible = "allwinner,sun8i-h3-display-engine";
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- allwinner,pipelines = <&mixer0>;
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+ allwinner,pipelines = <&mixer0>, <&mixer1>;
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status = "disabled";
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};
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@@ -139,11 +139,50 @@ ports {
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#size-cells = <0>;
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mixer0_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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reg = <1>;
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- mixer0_out_tcon0: endpoint {
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+ mixer0_out_tcon0: endpoint@0 {
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+ reg = <0>;
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remote-endpoint = <&tcon0_in_mixer0>;
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};
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+
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+ mixer0_out_tcon1: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&tcon1_in_mixer0>;
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+ };
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+ };
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+ };
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+ };
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+
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+ mixer1: mixer@1200000 {
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+ compatible = "allwinner,sun8i-h3-de2-mixer-1";
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+ reg = <0x01200000 0x100000>;
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+ clocks = <&display_clocks CLK_BUS_MIXER1>,
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+ <&display_clocks CLK_MIXER1>;
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+ clock-names = "bus",
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+ "mod";
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+ /* reset is added by SoC dtsi */
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ mixer1_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+
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+ mixer1_out_tcon0: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&tcon0_in_mixer1>;
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+ };
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+
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+ mixer1_out_tcon1: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&tcon1_in_mixer1>;
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+ };
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};
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};
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};
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@@ -172,11 +211,19 @@ ports {
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#size-cells = <0>;
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tcon0_in: port@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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reg = <0>;
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- tcon0_in_mixer0: endpoint {
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+ tcon0_in_mixer0: endpoint@0 {
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+ reg = <0>;
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remote-endpoint = <&mixer0_out_tcon0>;
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};
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+
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+ tcon0_in_mixer1: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&mixer1_out_tcon0>;
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+ };
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};
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tcon0_out: port@1 {
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@@ -192,6 +239,48 @@ tcon0_out_hdmi: endpoint@1 {
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};
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};
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+ tcon1: lcd-controller@1c0d000 {
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+ compatible = "allwinner,sun8i-h3-tcon-tv",
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+ "allwinner,sun8i-a83t-tcon-tv";
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+ reg = <0x01c0d000 0x1000>;
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+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TVE>;
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+ clock-names = "ahb", "tcon-ch1";
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+ resets = <&ccu RST_BUS_TCON1>;
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+ reset-names = "lcd";
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+
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+ ports {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ tcon1_in: port@0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <0>;
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+
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+ tcon1_in_mixer0: endpoint@0 {
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+ reg = <0>;
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+ remote-endpoint = <&mixer0_out_tcon1>;
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+ };
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+
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+ tcon1_in_mixer1: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&mixer1_out_tcon1>;
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+ };
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+ };
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+
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+ tcon1_out: port@1 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ reg = <1>;
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+
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+ tcon1_out_tve: endpoint@1 {
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+ reg = <1>;
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+ };
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+ };
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+ };
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+ };
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+
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mmc0: mmc@1c0f000 {
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/* compatible and clocks are in per SoC .dtsi file */
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reg = <0x01c0f000 0x1000>;
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diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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index d3caf27b6a55..31e67b91e4fa 100644
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--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
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@@ -184,6 +184,20 @@ ths: thermal-sensor@1c25000 {
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nvmem-cell-names = "calibration";
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#thermal-sensor-cells = <1>;
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};
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+
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+ tve: tv-encoder@1e40000 {
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+ compatible = "allwinner,sun50i-h5-tv-encoder";
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+ reg = <0x01e40000 0x1000>;
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+ clocks = <&ccu CLK_BUS_TVE>;
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+ resets = <&ccu RST_BUS_TVE>;
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+ status = "disabled";
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+
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+ port {
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+ tve_in_tcon1: endpoint {
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+ remote-endpoint = <&tcon1_out_tve>;
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+ };
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+ };
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+ };
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};
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thermal-zones {
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@@ -237,6 +251,10 @@ &mbus {
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compatible = "allwinner,sun50i-h5-mbus";
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};
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+&mixer1 {
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+ resets = <&display_clocks RST_MIXER1>;
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+};
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+
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&mmc0 {
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compatible = "allwinner,sun50i-h5-mmc",
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"allwinner,sun50i-a64-mmc";
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@@ -272,3 +290,7 @@ &rtc {
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&sid {
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compatible = "allwinner,sun50i-h5-sid";
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};
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+
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+&tcon1_out_tve {
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+ remote-endpoint = <&tve_in_tcon1>;
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+};
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diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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index 74274c17efb3..c4f4ba836408 100644
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--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
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@@ -463,8 +463,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
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CLK_SET_RATE_PARENT);
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static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
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-static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
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- 0x120, 0, 4, 24, 3, BIT(31), 0);
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+struct ccu_div tve_clk = {
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+ .enable = BIT(31),
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+ .div = _SUNXI_CCU_DIV(0, 4),
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+ .mux = _SUNXI_CCU_MUX(24, 3),
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+ .fixed_post_div = 16,
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+ .common = {
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+ .reg = 0x120,
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+ .features = CCU_FEATURE_FIXED_POSTDIV,
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+ .hw.init = CLK_HW_INIT_PARENTS("tve", tve_parents,
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+ &ccu_div_ops, 0),
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+ },
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+};
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static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
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static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
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diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
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index ec65d9d59de7..d2235d5a7416 100644
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--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
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+++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
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@@ -10,6 +10,7 @@
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#include <linux/component.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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+#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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@@ -159,6 +160,11 @@ struct tv_mode {
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const struct resync_parameters *resync_params;
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};
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+struct sun4i_tv_quirks {
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+ unsigned int calibration;
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+ unsigned int unknown : 1;
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+};
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+
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struct sun4i_tv {
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struct drm_connector connector;
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struct drm_encoder encoder;
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@@ -419,7 +425,7 @@ static const struct regmap_config sun4i_tv_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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- .max_register = SUN4I_TVE_WSS_DATA2_REG,
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+ .max_register = 0x400,
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.name = "tv-encoder",
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};
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@@ -429,13 +435,19 @@ static int sun4i_tv_bind(struct device *dev, struct device *master,
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struct platform_device *pdev = to_platform_device(dev);
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struct drm_device *drm = data;
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struct sun4i_drv *drv = drm->dev_private;
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+ const struct sun4i_tv_quirks *quirks;
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struct sun4i_tv *tv;
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void __iomem *regs;
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int ret;
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+ quirks = of_device_get_match_data(dev);
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+ if (!quirks)
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+ return -EINVAL;
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+
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tv = devm_kzalloc(dev, sizeof(*tv), GFP_KERNEL);
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if (!tv)
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return -ENOMEM;
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+
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tv->drv = drv;
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dev_set_drvdata(dev, tv);
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@@ -472,6 +484,11 @@ static int sun4i_tv_bind(struct device *dev, struct device *master,
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}
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clk_prepare_enable(tv->clk);
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+ if (quirks->calibration)
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+ regmap_write(tv->regs, 0x304, quirks->calibration);
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+ if (quirks->unknown)
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+ regmap_write(tv->regs, 0x30c, 0x00101110);
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+
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drm_encoder_helper_add(&tv->encoder,
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&sun4i_tv_helper_funcs);
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ret = drm_simple_encoder_init(drm, &tv->encoder,
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@@ -551,8 +568,22 @@ static void sun4i_tv_remove(struct platform_device *pdev)
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component_del(&pdev->dev, &sun4i_tv_ops);
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}
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+static const struct sun4i_tv_quirks a10_quirks = {
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+};
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+
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+static const struct sun4i_tv_quirks h3_quirks = {
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+ .calibration = 0x02000c00,
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+};
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+
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+static const struct sun4i_tv_quirks h5_quirks = {
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+ .calibration = 0x02850000,
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+ .unknown = 1,
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+};
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+
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static const struct of_device_id sun4i_tv_of_table[] = {
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- { .compatible = "allwinner,sun4i-a10-tv-encoder" },
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+ { .compatible = "allwinner,sun4i-a10-tv-encoder", .data = &a10_quirks },
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+ { .compatible = "allwinner,sun8i-h3-tv-encoder", .data = &h3_quirks },
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+ { .compatible = "allwinner,sun50i-h5-tv-encoder", .data = &h5_quirks },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sun4i_tv_of_table);
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diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
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index 8e32d0b24ac9..854f5ab76463 100644
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--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
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+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
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@@ -36,6 +36,12 @@ struct de2_fmt_info {
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u32 de2_fmt;
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};
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+static const u32 sun8i_rgb2yuv_coef[12] = {
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+ 0x00000107, 0x00000204, 0x00000064, 0x00004200,
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+ 0x00001f68, 0x00001ed6, 0x000001c2, 0x00020200,
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+ 0x000001c2, 0x00001e87, 0x00001fb7, 0x00020200,
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+};
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+
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static const struct de2_fmt_info de2_formats[] = {
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{
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.drm_fmt = DRM_FORMAT_ARGB8888,
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@@ -369,11 +375,30 @@ static u32 *sun8i_mixer_get_supported_fmts(struct sunxi_engine *engine, u32 *num
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return formats;
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}
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+static void sun8i_mixer_apply_color_correction(struct sunxi_engine *engine)
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+{
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+ DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
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+
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+ regmap_bulk_write(engine->regs, SUN8I_MIXER_DCSC_COEF_REG(0),
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+ sun8i_rgb2yuv_coef, 12);
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+ regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 1);
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+}
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+
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+static void sun8i_mixer_disable_color_correction(struct sunxi_engine *engine)
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+{
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+ DRM_DEBUG_DRIVER("Disabling color correction\n");
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+
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+ /* Disable color correction */
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+ regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 0);
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+}
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+
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static const struct sunxi_engine_ops sun8i_engine_ops = {
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.commit = sun8i_mixer_commit,
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.layers_init = sun8i_layers_init,
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.mode_set = sun8i_mixer_mode_set,
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.get_supported_fmts = sun8i_mixer_get_supported_fmts,
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+ .apply_color_correction = sun8i_mixer_apply_color_correction,
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+ .disable_color_correction = sun8i_mixer_disable_color_correction,
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};
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static const struct regmap_config sun8i_mixer_regmap_config = {
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@@ -631,6 +656,15 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
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.vi_num = 1,
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};
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+static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = {
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+ .ccsc = 1,
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+ .mod_rate = 432000000,
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+ .scaler_mask = 0x3,
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+ .scanline_yuv = 2048,
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+ .ui_num = 1,
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+ .vi_num = 1,
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+};
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+
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static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
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.ccsc = CCSC_MIXER0_LAYOUT,
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.mod_rate = 297000000,
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@@ -718,6 +752,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
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.compatible = "allwinner,sun8i-h3-de2-mixer-0",
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.data = &sun8i_h3_mixer0_cfg,
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},
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+ {
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+ .compatible = "allwinner,sun8i-h3-de2-mixer-1",
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+ .data = &sun8i_h3_mixer1_cfg,
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+ },
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{
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.compatible = "allwinner,sun8i-r40-de2-mixer-0",
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.data = &sun8i_r40_mixer0_cfg,
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diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
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index 13401643c7bf..5951adb66e69 100644
|
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--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
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|
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
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|
@@ -118,6 +118,10 @@
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|
/* format 20 is packed YVU444 10-bit */
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|
/* format 21 is packed YUV444 10-bit */
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|
|
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+/* The DCSC sub-engine is used to do color space conversation */
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+#define SUN8I_MIXER_DCSC_EN 0xb0000
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+#define SUN8I_MIXER_DCSC_COEF_REG(x) (0xb0010 + 0x4 * (x))
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|
+
|
|
/*
|
|
* Sub-engines listed bellow are unused for now. The EN registers are here only
|
|
* to be used to disable these sub-engines.
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|
@@ -128,7 +132,6 @@
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|
#define SUN8I_MIXER_PEAK_EN 0xa6000
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#define SUN8I_MIXER_ASE_EN 0xa8000
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#define SUN8I_MIXER_FCC_EN 0xaa000
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|
-#define SUN8I_MIXER_DCSC_EN 0xb0000
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|
|
|
#define SUN50I_MIXER_FCE_EN 0x70000
|
|
#define SUN50I_MIXER_PEAK_EN 0x70800
|
|
--
|
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2.42.0
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