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https://github.com/libretro/Lakka-LibreELEC.git
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162 lines
5.9 KiB
Diff
162 lines
5.9 KiB
Diff
From 38f1f4ecd038628f4ce7a47114455123e5db3367 Mon Sep 17 00:00:00 2001
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From: Sandor Yu <Sandor.yu@nxp.com>
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Date: Wed, 30 Dec 2020 16:02:52 +0800
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Subject: [PATCH 37/49] MLK-25199-1: drm: mhdp: Add hdmi phy reset/poweroff
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function
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Add hdmi phy reset and power off function.
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Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
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Reviewed-by: Robby Cai <robby.cai@nxp.com>
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---
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drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c | 28 ++++++++++++++++++-
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drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h | 3 +-
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drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c | 4 +--
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drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c | 2 ++
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drivers/gpu/drm/imx/mhdp/cdns-mhdp-phy.h | 3 +-
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5 files changed, 35 insertions(+), 5 deletions(-)
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diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c
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index 120300e6a2df..212f3f4f1e26 100644
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--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c
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+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-hdmi-phy.c
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@@ -1,7 +1,7 @@
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/*
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* Cadence High-Definition Multimedia Interface (HDMI) driver
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*
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- * Copyright (C) 2019 NXP Semiconductor, Inc.
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+ * Copyright (C) 2019-2021 NXP Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -21,6 +21,7 @@
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#include <drm/bridge/cdns-mhdp.h>
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#include "cdns-mhdp-phy.h"
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+#include "cdns-mhdp-imx.h"
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/* HDMI TX clock control settings */
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struct hdmi_ctrl {
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@@ -746,6 +747,7 @@ int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *mhdp)
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DRM_ERROR("NO HDMI FW running\n");
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return -ENXIO;
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}
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+ imx8qm_phy_reset(0);
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/* Configure PHY */
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mhdp->hdmi.char_rate = hdmi_phy_cfg_ss28fdsoi(mhdp, mode);
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@@ -753,6 +755,7 @@ int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *mhdp)
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DRM_ERROR("failed to set phy pclock\n");
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return -EINVAL;
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}
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+ imx8qm_phy_reset(1);
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ret = hdmi_phy_power_up(mhdp);
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if (ret < 0)
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@@ -762,3 +765,26 @@ int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *mhdp)
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return true;
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}
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+
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+int cdns_hdmi_phy_shutdown(struct cdns_mhdp_device *mhdp)
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+{
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+ int timeout;
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+ u32 reg_val;
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+
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+ reg_val = cdns_phy_reg_read(mhdp, PHY_HDP_MODE_CTRL);
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+ reg_val &= 0xfff0;
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+ /* PHY_DP_MODE_CTL set to A3 power state*/
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+ cdns_phy_reg_write(mhdp, PHY_HDP_MODE_CTRL, reg_val | 0x8);
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+
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+ /* PHY_DP_MODE_CTL */
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+ timeout = 0;
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+ do {
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+ reg_val = cdns_phy_reg_read(mhdp, PHY_HDP_MODE_CTRL);
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+ DRM_INFO("Reg val is 0x%04x\n", reg_val);
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+ timeout++;
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+ msleep(100);
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+ } while (!(reg_val & (0x8 << 4)) && (timeout < 10)); /* Wait for A3 acknowledge */
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+
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+ DRM_INFO("hdmi phy shutdown complete\n");
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+ return 0;
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+}
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diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h
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index fc3247dada2d..a12005ae4c53 100644
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--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h
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+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx.h
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@@ -1,7 +1,7 @@
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/*
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* Cadence High-Definition Multimedia Interface (HDMI) driver
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*
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- * Copyright (C) 2019 NXP Semiconductor, Inc.
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+ * Copyright (C) 2019-2021 NXP Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -72,4 +72,5 @@ int cdns_mhdp_suspend_imx8qm(struct cdns_mhdp_device *mhdp);
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int cdns_mhdp_power_on_imx8qm(struct cdns_mhdp_device *mhdp);
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int cdns_mhdp_power_on_ls1028a(struct cdns_mhdp_device *mhdp);
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void cdns_mhdp_pclk_rate_ls1028a(struct cdns_mhdp_device *mhdp);
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+void imx8qm_phy_reset(u8 reset);
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#endif /* CDNS_MHDP_IMX_H_ */
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diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
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index 38f9defa42f8..46c0500da4c3 100644
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--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
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+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imx8qm.c
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@@ -1,5 +1,5 @@
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/*
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- * Copyright (c) 2019 NXP semiconductor, inc.
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+ * Copyright (c) 2019-2021 NXP semiconductor, inc.
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*
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* this program is free software; you can redistribute it and/or modify
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* it under the terms of the gnu general public license version 2 as
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@@ -102,7 +102,7 @@ static void imx8qm_pixel_link_sync_disable(u32 dual_mode)
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imx_sc_misc_set_control(handle, IMX_SC_R_DC_0, IMX_SC_C_SYNC_CTRL0, 0);
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}
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-static void imx8qm_phy_reset(u8 reset)
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+void imx8qm_phy_reset(u8 reset)
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{
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struct imx_sc_ipc *handle;
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diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c
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index 9fa0df74ad7c..4c4ce9d3c847 100644
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--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c
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+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-imxdrv.c
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@@ -22,6 +22,7 @@ static void cdns_mhdp_imx_encoder_disable(struct drm_encoder *encoder)
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struct drm_bridge *bridge = drm_bridge_chain_get_first_bridge(encoder);
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struct cdns_mhdp_device *mhdp = bridge->driver_private;
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+ cdns_hdmi_phy_shutdown(mhdp);
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cdns_mhdp_plat_call(mhdp, plat_init);
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}
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@@ -184,6 +185,7 @@ static int cdns_mhdp_imx_bind(struct device *dev, struct device *master,
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imx_mhdp->mhdp.plat_data = plat_data;
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imx_mhdp->mhdp.dev = dev;
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+ imx_mhdp->mhdp.drm_dev = drm;
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imx_mhdp->mhdp.bus_type = plat_data->bus_type;
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ret = plat_data->bind(pdev, encoder, &imx_mhdp->mhdp);
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/*
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diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-phy.h b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-phy.h
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index 5682b9fbc90f..9035f1f71eee 100644
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--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-phy.h
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+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-phy.h
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@@ -1,5 +1,5 @@
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/*
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- * Copyright (C) 2019 NXP Semiconductor, Inc.
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+ * Copyright (C) 2019-2021 NXP Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -152,4 +152,5 @@ bool cdns_hdmi_phy_video_valid_imx8mq(struct cdns_mhdp_device *hdp);
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bool cdns_hdmi_phy_video_valid_imx8qm(struct cdns_mhdp_device *hdp);
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int cdns_hdmi_phy_set_imx8mq(struct cdns_mhdp_device *hdp);
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int cdns_hdmi_phy_set_imx8qm(struct cdns_mhdp_device *hdp);
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+int cdns_hdmi_phy_shutdown(struct cdns_mhdp_device *mhdp);
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#endif /* _CDNS_MHDP_PHY_H */
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--
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2.29.2
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