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https://github.com/libretro/Lakka-LibreELEC.git
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59 lines
1.9 KiB
Diff
59 lines
1.9 KiB
Diff
From c789945d09e4c77eb30af1a8db1425cefab52080 Mon Sep 17 00:00:00 2001
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From: Sandor Yu <Sandor.yu@nxp.com>
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Date: Fri, 28 Aug 2020 10:09:12 +0800
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Subject: [PATCH 33/49] MLK-24601: drm: imx: mhdp: DP PHY support 1/2 lanes
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mode
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All four lanes should be configurated for 1/2/4 lanes modes in driver.
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The DP FW will power down unused PHY lanes after negotiation.
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Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
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Reviewed-by: Robby Cai <robby.cai@nxp.com>
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---
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drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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diff --git a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c
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index 5c75e7d40cc0..3d17840b0941 100644
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--- a/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c
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+++ b/drivers/gpu/drm/imx/mhdp/cdns-mhdp-dp-phy.c
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@@ -137,7 +137,7 @@ static void dp_aux_cfg(struct cdns_mhdp_device *mhdp)
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static void dp_phy_pma_cmn_cfg_24mhz(struct cdns_mhdp_device *mhdp)
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{
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int k;
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- u32 num_lanes = mhdp->dp.num_lanes;
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+ u32 num_lanes = 4;
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u16 val;
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val = cdns_phy_reg_read(mhdp, PHY_PMA_CMN_CTRL1);
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@@ -157,7 +157,7 @@ static void dp_phy_pma_cmn_cfg_24mhz(struct cdns_mhdp_device *mhdp)
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/* Valid for 24 MHz only */
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static void dp_phy_pma_cmn_pll0_24mhz(struct cdns_mhdp_device *mhdp)
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{
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- u32 num_lanes = mhdp->dp.num_lanes;
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+ u32 num_lanes = 4;
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u32 link_rate = mhdp->dp.rate;
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u16 val;
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int index, i, k;
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@@ -228,7 +228,7 @@ static void dp_phy_pma_cmn_pll0_24mhz(struct cdns_mhdp_device *mhdp)
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/* PMA common configuration for 27MHz */
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static void dp_phy_pma_cmn_cfg_27mhz(struct cdns_mhdp_device *mhdp)
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{
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- u32 num_lanes = mhdp->dp.num_lanes;
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+ u32 num_lanes = 4;
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u16 val;
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int k;
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@@ -279,7 +279,7 @@ static void dp_phy_pma_cmn_cfg_27mhz(struct cdns_mhdp_device *mhdp)
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static void dp_phy_pma_cmn_pll0_27mhz(struct cdns_mhdp_device *mhdp)
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{
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- u32 num_lanes = mhdp->dp.num_lanes;
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+ u32 num_lanes = 4;
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u32 link_rate = mhdp->dp.rate;
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u16 val;
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int index, i, k;
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--
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2.29.2
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