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35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From 04a71f1da60e51f277d4979c698e52cacb028666 Mon Sep 17 00:00:00 2001
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From: Sandor Yu <Sandor.yu@nxp.com>
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Date: Mon, 14 Sep 2020 15:06:35 +0800
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Subject: [PATCH 10/49] MLK-24770: drm: mhdp: Sync DPTX capability with Cadence
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sample code
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Sync the max vswing and pre-emphasis setting with Cadence sample code.
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The max vswing is VOLTAGE_LEVEL_3 and
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the max pre-emphasis is PRE_EMPHASIS_LEVEL_2 now.
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Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
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Reviewed-by: Robby Cai <robby.cai@nxp.com>
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---
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drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
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index 890add9b7c67..2043016f176b 100644
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--- a/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
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+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp-common.c
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@@ -445,8 +445,8 @@ int cdns_mhdp_set_host_cap(struct cdns_mhdp_device *mhdp)
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msg[0] = drm_dp_link_rate_to_bw_code(mhdp->dp.rate);
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msg[1] = mhdp->dp.num_lanes | SCRAMBLER_EN;
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- msg[2] = VOLTAGE_LEVEL_2;
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- msg[3] = PRE_EMPHASIS_LEVEL_3;
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+ msg[2] = VOLTAGE_LEVEL_3;
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+ msg[3] = PRE_EMPHASIS_LEVEL_2;
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msg[4] = PTS1 | PTS2 | PTS3 | PTS4;
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msg[5] = FAST_LT_NOT_SUPPORT;
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msg[6] = mhdp->lane_mapping;
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--
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2.29.2
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