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https://github.com/libretro/Lakka-LibreELEC.git
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65 lines
1.9 KiB
Diff
65 lines
1.9 KiB
Diff
From eba616b4f08a69c3398d6fd32d19a8896d36db50 Mon Sep 17 00:00:00 2001
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From: OtherCrashOverride <OtherCrashOverride@users.noreply.github.com>
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Date: Sun, 9 Apr 2017 17:31:25 +0000
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Subject: [PATCH 03/25] MEMEKA: drm/exynos/mixer: never blend the base layer
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On Exynos there is a solid color plane that is logically below all the other display planes.
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This causes display artifacts due to alpha. The patch disables blending the base plane with
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the solid color plane (no alpha).
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Reviewed-by: memeka <mihailescu2m@gmail.com>
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Signed-off-by: memeka <mihailescu2m@gmail.com>
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---
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drivers/gpu/drm/exynos/exynos_mixer.c | 33 +++++++++++++++------------
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1 file changed, 18 insertions(+), 15 deletions(-)
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diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
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index 21b726baedea..c1a527fa1df8 100644
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--- a/drivers/gpu/drm/exynos/exynos_mixer.c
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+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
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@@ -315,23 +315,26 @@ static void mixer_cfg_gfx_blend(struct mixer_context *ctx, unsigned int win,
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u32 val;
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val = MXR_GRP_CFG_COLOR_KEY_DISABLE; /* no blank key */
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- switch (pixel_alpha) {
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- case DRM_MODE_BLEND_PIXEL_NONE:
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- break;
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- case DRM_MODE_BLEND_COVERAGE:
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- val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
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- break;
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- case DRM_MODE_BLEND_PREMULTI:
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- default:
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- val |= MXR_GRP_CFG_BLEND_PRE_MUL;
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- val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
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- break;
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- }
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+ if (win) {
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+ switch (pixel_alpha) {
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+ case DRM_MODE_BLEND_PIXEL_NONE:
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+ break;
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+ case DRM_MODE_BLEND_COVERAGE:
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+ val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
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+ break;
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+ case DRM_MODE_BLEND_PREMULTI:
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+ default:
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+ val |= MXR_GRP_CFG_BLEND_PRE_MUL;
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+ val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
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+ break;
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+ }
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- if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
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- val |= MXR_GRP_CFG_WIN_BLEND_EN;
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- val |= win_alpha;
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+ if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
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+ val |= MXR_GRP_CFG_WIN_BLEND_EN;
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+ val |= win_alpha;
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+ }
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}
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+
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mixer_reg_writemask(ctx, MXR_GRAPHIC_CFG(win),
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val, MXR_GRP_CFG_MISC_MASK);
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}
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--
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2.17.1
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