forked from Openwrt/openwrt
203 lines
7.7 KiB
Diff
203 lines
7.7 KiB
Diff
--- a/gcc/config/mips/mips-cpus.def 2017-01-01 10:07:43.905435000 -0200
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+++ b/gcc/config/mips/mips-cpus.def 2019-06-28 11:37:27.632872839 -0300
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@@ -171,3 +171,8 @@
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/* MIPS64 Release 6 processors. */
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MIPS_CPU ("i6400", PROCESSOR_I6400, 69, 0)
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+
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+/* Lexra processors */
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+MIPS_CPU ("lx4380", PROCESSOR_LX4380, 1, 0)
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+MIPS_CPU ("lx5280", PROCESSOR_LX5280, 1, 0)
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+MIPS_CPU ("lx5380", PROCESSOR_LX5380, 1, 0)
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--- a/gcc/config/mips/mips-tables.opt 2017-01-01 10:07:43.905435000 -0200
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+++ b/gcc/config/mips/mips-tables.opt 2019-06-28 11:53:08.281445803 -0300
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@@ -696,3 +696,12 @@
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EnumValue
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Enum(mips_arch_opt_value) String(i6400) Value(102) Canonical
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+EnumValue
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+Enum(mips_arch_opt_value) String(lx4380) Value(103) Canonical
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+
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+EnumValue
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+Enum(mips_arch_opt_value) String(lx5280) Value(104) Canonical
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+
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+EnumValue
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+Enum(mips_arch_opt_value) String(lx5380) Value(105) Canonical
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+
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--- a/gcc/config/mips/mips.c 2019-06-21 15:50:27.070510816 -0300
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+++ b/gcc/config/mips/mips.c 2019-06-21 11:56:30.260810586 -0300
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@@ -19669,6 +19669,10 @@
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if (mips_arch_info == 0)
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mips_set_architecture (mips_default_arch ());
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+ /* flag_fix_bdsl only works for Taroko processors */
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+ if (flag_fix_bdsl && !TARGET_LEXRA)
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+ flag_fix_bdsl = false;
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+
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if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
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error ("%<-march=%s%> is not compatible with the selected ABI",
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mips_arch_info->name);
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--- a/gcc/config/mips/mips.h 2017-01-19 23:05:25.742100000 -0200
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+++ b/gcc/config/mips/mips.h 2019-06-28 11:49:15.064453334 -0300
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@@ -287,6 +287,12 @@
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#define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
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#define TARGET_XLP (mips_arch == PROCESSOR_XLP)
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+#define TARGET_LX5380 (mips_arch == PROCESSOR_LX5380)
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+#define TARGET_LX5280 (mips_arch == PROCESSOR_LX5280)
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+#define TARGET_LX4380 (mips_arch == PROCESSOR_LX4380)
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+#define TARGET_LEXRA (mips_arch == PROCESSOR_LX4380 \
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+ || mips_arch == PROCESSOR_LX5280 || TARGET_LX5380)
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+
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/* Scheduling target defines. */
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#define TUNE_20KC (mips_tune == PROCESSOR_20KC)
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#define TUNE_24K (mips_tune == PROCESSOR_24KC \
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@@ -299,7 +303,7 @@
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#define TUNE_LOONGSON_2EF (mips_tune == PROCESSOR_LOONGSON_2E \
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|| mips_tune == PROCESSOR_LOONGSON_2F)
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#define TUNE_LOONGSON_3A (mips_tune == PROCESSOR_LOONGSON_3A)
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-#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
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+#define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000 || TARGET_LEXRA)
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#define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
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#define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
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#define TUNE_MIPS4120 (mips_tune == PROCESSOR_R4120)
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@@ -641,6 +645,14 @@
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builtin_define ("__mips_no_lxc1_sxc1"); \
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if (!ISA_HAS_UNFUSED_MADD4 && !ISA_HAS_FUSED_MADD4) \
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builtin_define ("__mips_no_madd4"); \
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+ if (TARGET_LEXRA) \
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+ builtin_define ("__mlexra"); \
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+ if (TARGET_LX4380) \
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+ builtin_define ("__mlx4380"); \
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+ if (TARGET_LX5380) \
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+ builtin_define ("__mlx5380"); \
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+ if (flag_fix_bdsl) \
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+ builtin_define ("__FIX_BDSL__"); \
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} \
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while (0)
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@@ -799,6 +807,7 @@
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"%{mhard-float|msoft-float|mno-float|march=mips*:; \
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march=vr41*|march=m4k|march=4k*|march=24kc|march=24kec \
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|march=34kc|march=34kn|march=74kc|march=1004kc|march=5kc \
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+ |march=lx* \
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|march=m14k*|march=m5101|march=octeon|march=xlr: -msoft-float; \
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march=*: -mhard-float}"
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@@ -1011,7 +1020,8 @@
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ST Loongson 2E/2F. */
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#define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE \
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|| TARGET_MIPS5900 \
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- || TARGET_LOONGSON_2EF)
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+ || TARGET_LOONGSON_2EF \
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+ || (!TARGET_MIPS16 && TARGET_LEXRA))
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/* ISA has LDC1 and SDC1. */
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#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 \
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@@ -1255,7 +1265,7 @@
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#define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16)
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/* ISA includes sync. */
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-#define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16)
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+#define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900 || TARGET_LX5380) && !TARGET_MIPS16)
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#define GENERATE_SYNC \
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(target_flags_explicit & MASK_LLSC \
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? TARGET_LLSC && !TARGET_MIPS16 \
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@@ -1264,7 +1274,7 @@
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/* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
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because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
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instructions. */
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-#define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
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+#define ISA_HAS_LL_SC ((mips_isa >= 2 || TARGET_LX5380) && !TARGET_MIPS5900 && !TARGET_MIPS16)
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#define GENERATE_LL_SC \
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(target_flags_explicit & MASK_LLSC \
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? TARGET_LLSC && !TARGET_MIPS16 \
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@@ -1396,6 +1406,9 @@
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#undef CC1_SPEC
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#define CC1_SPEC "\
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+%{mlx4380:-march=lx4380} \
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+%{mlx5280:-march=lx5280} \
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+%{mlx5380:-march=lx5380} \
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%{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
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%(subtarget_cc1_spec)"
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--- a/gcc/config/mips/mips.md 2017-04-19 01:52:54.447911000 -0300
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+++ b/gcc/config/mips/mips.md 2019-06-28 11:52:19.537373476 -0300
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@@ -69,6 +69,9 @@
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p5600
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m5100
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i6400
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+ lx4380
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+ lx5280
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+ lx5380
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])
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(define_c_enum "unspec" [
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@@ -757,9 +760,13 @@
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;; Can the instruction be put into a delay slot?
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(define_attr "can_delay" "no,yes"
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- (if_then_else (and (eq_attr "type" "!branch,call,jump")
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- (eq_attr "hazard" "none")
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- (match_test "get_attr_insn_count (insn) == 1"))
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+ (if_then_else (and (ior (eq (symbol_ref "TARGET_MIPS16") (const_int 0))
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+ (eq (symbol_ref "flag_fix_bdsl") (const_int 0)))
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+ (ior (eq_attr "type" "!load")
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+ (eq (symbol_ref "flag_fix_bdsl") (const_int 0)))
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+ (and (eq_attr "type" "!branch,call,jump")
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+ (eq_attr "hazard" "none")
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+ (match_test "get_attr_insn_count (insn) == 1")))
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(const_string "yes")
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(const_string "no")))
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@@ -4339,7 +4346,7 @@
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(unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
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(match_operand:QI 2 "memory_operand" "ZC")]
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UNSPEC_LOAD_LEFT))]
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- "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
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+ "!TARGET_MIPS16 && !TARGET_LX5280 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
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"<load>l\t%0,%2"
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[(set_attr "move_type" "load")
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(set_attr "mode" "<MODE>")])
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@@ -4350,7 +4357,7 @@
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(match_operand:QI 2 "memory_operand" "ZC")
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(match_operand:GPR 3 "register_operand" "0")]
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UNSPEC_LOAD_RIGHT))]
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- "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
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+ "!TARGET_MIPS16 && !TARGET_LX5280 && mips_mem_fits_mode_p (<MODE>mode, operands[1])"
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"<load>r\t%0,%2"
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[(set_attr "move_type" "load")
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(set_attr "mode" "<MODE>")])
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@@ -4360,7 +4367,7 @@
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(unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
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(match_operand:QI 2 "memory_operand" "ZC")]
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UNSPEC_STORE_LEFT))]
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- "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
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+ "!TARGET_MIPS16 && !TARGET_LX5280 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
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"<store>l\t%z1,%2"
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[(set_attr "move_type" "store")
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(set_attr "mode" "<MODE>")])
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@@ -4371,7 +4378,7 @@
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(match_operand:QI 2 "memory_operand" "ZC")
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(match_dup 0)]
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UNSPEC_STORE_RIGHT))]
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- "!TARGET_MIPS16 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
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+ "!TARGET_MIPS16 && !TARGET_LX5280 && mips_mem_fits_mode_p (<MODE>mode, operands[0])"
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"<store>r\t%z1,%2"
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[(set_attr "move_type" "store")
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(set_attr "mode" "<MODE>")])
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--- a/gcc/config/mips/mips.opt 2017-04-10 10:44:39.662699000 -0300
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+++ b/gcc/config/mips/mips.opt 2019-06-21 14:43:00.817410739 -0300
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@@ -315,6 +315,10 @@
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Target Report Var(TARGET_MCU)
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Use MCU instructions.
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+mno-bdsl
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+Target Report Var(flag_fix_bdsl) Init(0)
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+Forbid the use of load instructions in the branch delay slots for all cases
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+
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mno-flush-func
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Target RejectNegative
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Do not use a cache-flushing function before calling stack trampolines.
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