forked from Openwrt/openwrt
142 lines
3.2 KiB
Plaintext
142 lines
3.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "realtek,rtl819x-soc";
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cpuintc: cpuintc {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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refclk: refclk {
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/* 25Mhz default clock */
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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clk40: clk40 {
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/* 40Mhz alternative clock */
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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};
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soc {
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compatible = "simple-bus";
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ranges = <0x0 0x18000000 0x10000>;
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#address-cells = <1>;
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#size-cells = <1>;
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sysc: system-controller@0 {
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compatible = "realtek,rtl819x-sysc";
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reg = <0x0 0x1000>;
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};
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memc: memory-controller@1000 {
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compatible = "realtek,rtl819x-memc";
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reg = <0x1000 0x100>;
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};
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uartlite: serial@2000 {
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compatible = "realtek,rtl819x-uart", "ns16550a";
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reg = <0x2000 0x20>;
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interrupt-parent = <&intc>;
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interrupts = <12>;
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reg-shift = <2>;
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clock-frequency = <200000000>;
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};
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intc: intc@3000 {
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compatible = "realtek,rtl819x-intc";
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reg = <0x3000 0x100>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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timer: timer-controller@3100 {
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compatible = "realtek,rtl819x-timer";
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reg = <0x3100 0x20>;
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interrupt-parent = <&cpuintc>;
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interrupts = <7>;
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clocks = <&refclk>;
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};
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gpio0: gpio-controller@3500 {
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compatible = "realtek,realtek-gpio";
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reg = <0x3500 0x1c>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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gpio1: gpio-controller@351C {
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compatible = "realtek,realtek-gpio";
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reg = <0x351C 0x1c>;
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gpio-controller;
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#gpio-cells = <2>;
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status = "disabled";
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};
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spi0: spi@1200 {
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compatible = "realtek,rtl819x-spi";
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reg = <0x1200 0x10>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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pcie0: pcie-controller@18b00000 {
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compatible = "realtek,rtl8196b-pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0 255>;
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reg = <0x18b00000 0x1000>, /* RC CFG */
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<0x18b01000 0x1000>, /* RC CFG EXT */
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<0x18b10000 0x1000>, /* DEV CFG0 (EP) */
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<0x18b11000 0x1000>; /* DEV CFG1 (EP) */
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reg-names = "rc_cfg_base", "rc_ext_base", "dev_cfg0_base", "dev_cfg1_base";
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ranges = <0x02000000 0 0x00000000 0x19000000 0 0x01000000 /* pci memory */
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0x01000000 0 0x00000000 0x18c00000 0 0x00200000>; /* io space */
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interrupt-parent = <&cpuintc>;
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interrupts = <5>;
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clocks = <&refclk>;
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status = "disabled";
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};
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pcie1: pcie-controller@18b20000 {
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compatible = "realtek,rtl8196b-pci";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0 255>;
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reg = <0x18b20000 0x1000>, /* RC CFG */
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<0x18b21000 0x1000>, /* RC CFG EXT */
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<0x18b30000 0x1000>, /* DEV CFG0 (EP) */
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<0x18b31000 0x1000>; /* DEV CFG1 (EP) */
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reg-names = "rc_cfg_base", "rc_ext_base", "dev_cfg0_base", "dev_cfg1_base";
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ranges = <0x02000000 0 0x00000000 0x1a000000 0 0x01000000 /* pci memory */
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0x01000000 0 0x00000000 0x18e00000 0 0x00200000>; /* io space */
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interrupt-parent = <&cpuintc>;
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interrupts = <6>;
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clocks = <&refclk>;
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status = "disabled";
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};
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};
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