657 lines
20 KiB
C
657 lines
20 KiB
C
/*
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* I2O kernel space accessible structures/APIs
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*
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* (c) Copyright 1999, 2000 Red Hat Software
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*************************************************************************
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*
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* This header file defined the I2O APIs/structures for use by
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* the I2O kernel modules.
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*
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*/
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#ifndef _I2O_H
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#define _I2O_H
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#ifdef __KERNEL__ /* This file to be included by kernel only */
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#include <linux/i2o-dev.h>
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/* How many different OSM's are we allowing */
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#define MAX_I2O_MODULES 64
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/* How many OSMs can register themselves for device status updates? */
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#define I2O_MAX_MANAGERS 4
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#include <asm/semaphore.h> /* Needed for MUTEX init macros */
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#include <linux/config.h>
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#include <linux/notifier.h>
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#include <asm/atomic.h>
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/*
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* Message structures
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*/
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struct i2o_message
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{
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u8 version_offset;
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u8 flags;
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u16 size;
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u32 target_tid:12;
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u32 init_tid:12;
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u32 function:8;
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u32 initiator_context;
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/* List follows */
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};
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/*
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* Each I2O device entity has one or more of these. There is one
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* per device.
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*/
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struct i2o_device
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{
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i2o_lct_entry lct_data; /* Device LCT information */
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u32 flags;
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int i2oversion; /* I2O version supported. Actually
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* there should be high and low
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* version */
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struct proc_dir_entry *proc_entry; /* /proc dir */
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/* Primary user */
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struct i2o_handler *owner;
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/* Management users */
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struct i2o_handler *managers[I2O_MAX_MANAGERS];
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int num_managers;
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struct i2o_controller *controller; /* Controlling IOP */
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struct i2o_device *next; /* Chain */
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struct i2o_device *prev;
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char dev_name[8]; /* linux /dev name if available */
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};
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/*
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* Resource data for each PCI I2O controller
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*/
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struct i2o_pci
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{
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int irq;
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int short_req:1; /* Use small block sizes */
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int dpt:1; /* Don't quiesce */
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int promise:1; /* Promise controller */
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#ifdef CONFIG_MTRR
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int mtrr_reg0;
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int mtrr_reg1;
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#endif
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};
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/*
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* Transport types supported by I2O stack
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*/
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#define I2O_TYPE_PCI 0x01 /* PCI I2O controller */
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/*
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* Each I2O controller has one of these objects
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*/
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struct i2o_controller
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{
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struct pci_dev *pdev; /* PCI device */
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char name[16];
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int unit;
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int type;
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int enabled;
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struct notifier_block *event_notifer; /* Events */
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atomic_t users;
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struct i2o_device *devices; /* I2O device chain */
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struct i2o_controller *next; /* Controller chain */
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unsigned long post_port; /* Inbout port address */
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unsigned long reply_port; /* Outbound port address */
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unsigned long irq_mask; /* Interrupt register address */
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/* Dynamic LCT related data */
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struct semaphore lct_sem;
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int lct_pid;
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int lct_running;
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i2o_status_block *status_block; /* IOP status block */
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i2o_lct *lct; /* Logical Config Table */
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i2o_lct *dlct; /* Temp LCT */
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i2o_hrt *hrt; /* HW Resource Table */
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unsigned long mem_offset; /* MFA offset */
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unsigned long mem_phys; /* MFA physical */
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int battery:1; /* Has a battery backup */
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int io_alloc:1; /* An I/O resource was allocated */
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int mem_alloc:1; /* A memory resource was allocated */
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struct resource io_resource; /* I/O resource allocated to the IOP */
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struct resource mem_resource; /* Mem resource allocated to the IOP */
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struct proc_dir_entry *proc_entry; /* /proc dir */
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union { /* Bus information */
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struct i2o_pci pci;
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} bus;
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/* Bus specific destructor */
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void (*destructor)(struct i2o_controller *);
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/* Bus specific attach/detach */
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int (*bind)(struct i2o_controller *, struct i2o_device *);
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/* Bus specific initiator */
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int (*unbind)(struct i2o_controller *, struct i2o_device *);
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/* Bus specific enable/disable */
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void (*bus_enable)(struct i2o_controller *);
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void (*bus_disable)(struct i2o_controller *);
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void *page_frame; /* Message buffers */
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dma_addr_t page_frame_map; /* Cache map */
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};
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/*
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* OSM resgistration block
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*
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* Each OSM creates at least one of these and registers it with the
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* I2O core through i2o_register_handler. An OSM may want to
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* register more than one if it wants a fast path to a reply
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* handler by having a separate initiator context for each
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* class function.
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*/
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struct i2o_handler
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{
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/* Message reply handler */
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void (*reply)(struct i2o_handler *, struct i2o_controller *,
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struct i2o_message *);
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/* New device notification handler */
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void (*new_dev_notify)(struct i2o_controller *, struct i2o_device *);
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/* Device deltion handler */
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void (*dev_del_notify)(struct i2o_controller *, struct i2o_device *);
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/* Reboot notification handler */
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void (*reboot_notify)(void);
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char *name; /* OSM name */
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int context; /* Low 8 bits of the transaction info */
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u32 class; /* I2O classes that this driver handles */
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/* User data follows */
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};
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#ifdef MODULE
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/*
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* Used by bus specific modules to communicate with the core
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*
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* This is needed because the bus modules cannot make direct
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* calls to the core as this results in the i2o_bus_specific_module
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* being dependent on the core, not the otherway around.
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* In that case, a 'modprobe i2o_lan' loads i2o_core & i2o_lan,
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* but _not_ i2o_pci...which makes the whole thing pretty useless :)
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*
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*/
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struct i2o_core_func_table
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{
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int (*install)(struct i2o_controller *);
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int (*activate)(struct i2o_controller *);
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struct i2o_controller *(*find)(int);
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void (*unlock)(struct i2o_controller *);
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void (*run_queue)(struct i2o_controller * c);
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int (*delete)(struct i2o_controller *);
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};
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#endif /* MODULE */
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/*
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* I2O System table entry
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*
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* The system table contains information about all the IOPs in the
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* system. It is sent to all IOPs so that they can create peer2peer
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* connections between them.
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*/
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struct i2o_sys_tbl_entry
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{
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u16 org_id;
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u16 reserved1;
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u32 iop_id:12;
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u32 reserved2:20;
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u16 seg_num:12;
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u16 i2o_version:4;
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u8 iop_state;
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u8 msg_type;
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u16 frame_size;
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u16 reserved3;
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u32 last_changed;
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u32 iop_capabilities;
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u32 inbound_low;
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u32 inbound_high;
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};
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struct i2o_sys_tbl
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{
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u8 num_entries;
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u8 version;
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u16 reserved1;
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u32 change_ind;
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u32 reserved2;
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u32 reserved3;
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struct i2o_sys_tbl_entry iops[0];
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};
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/*
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* Messenger inlines
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*/
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static inline u32 I2O_POST_READ32(struct i2o_controller *c)
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{
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return readl(c->post_port);
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}
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static inline void I2O_POST_WRITE32(struct i2o_controller *c, u32 val)
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{
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writel(val, c->post_port);
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}
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static inline u32 I2O_REPLY_READ32(struct i2o_controller *c)
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{
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return readl(c->reply_port);
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}
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static inline void I2O_REPLY_WRITE32(struct i2o_controller *c, u32 val)
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{
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writel(val, c->reply_port);
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}
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static inline u32 I2O_IRQ_READ32(struct i2o_controller *c)
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{
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return readl(c->irq_mask);
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}
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static inline void I2O_IRQ_WRITE32(struct i2o_controller *c, u32 val)
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{
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writel(val, c->irq_mask);
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}
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static inline void i2o_post_message(struct i2o_controller *c, u32 m)
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{
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/* The second line isnt spurious - thats forcing PCI posting */
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I2O_POST_WRITE32(c, m);
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(void) I2O_IRQ_READ32(c);
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}
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static inline void i2o_flush_reply(struct i2o_controller *c, u32 m)
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{
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I2O_REPLY_WRITE32(c, m);
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}
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/*
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* Endian handling wrapped into the macro - keeps the core code
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* cleaner.
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*/
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#define i2o_raw_writel(val, mem) __raw_writel(cpu_to_le32(val), mem)
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extern struct i2o_controller *i2o_find_controller(int);
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extern void i2o_unlock_controller(struct i2o_controller *);
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extern struct i2o_controller *i2o_controller_chain;
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extern int i2o_num_controllers;
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extern int i2o_status_get(struct i2o_controller *);
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extern int i2o_install_handler(struct i2o_handler *);
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extern int i2o_remove_handler(struct i2o_handler *);
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extern int i2o_claim_device(struct i2o_device *, struct i2o_handler *);
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extern int i2o_release_device(struct i2o_device *, struct i2o_handler *);
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extern int i2o_device_notify_on(struct i2o_device *, struct i2o_handler *);
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extern int i2o_device_notify_off(struct i2o_device *,
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struct i2o_handler *);
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extern int i2o_post_this(struct i2o_controller *, u32 *, int);
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extern int i2o_post_wait(struct i2o_controller *, u32 *, int, int);
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extern int i2o_post_wait_mem(struct i2o_controller *, u32 *, int, int,
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void *, void *);
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extern int i2o_query_scalar(struct i2o_controller *, int, int, int, void *,
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int);
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extern int i2o_set_scalar(struct i2o_controller *, int, int, int, void *,
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int);
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extern int i2o_query_table(int, struct i2o_controller *, int, int, int,
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void *, int, void *, int);
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extern int i2o_clear_table(struct i2o_controller *, int, int);
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extern int i2o_row_add_table(struct i2o_controller *, int, int, int,
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void *, int);
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extern int i2o_issue_params(int, struct i2o_controller *, int, void *, int,
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void *, int);
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extern int i2o_event_register(struct i2o_controller *, u32, u32, u32, u32);
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extern int i2o_event_ack(struct i2o_controller *, u32 *);
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extern void i2o_report_status(const char *, const char *, u32 *);
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extern void i2o_dump_message(u32 *);
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extern const char *i2o_get_class_name(int);
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extern int i2o_install_controller(struct i2o_controller *);
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extern int i2o_activate_controller(struct i2o_controller *);
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extern void i2o_run_queue(struct i2o_controller *);
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extern int i2o_delete_controller(struct i2o_controller *);
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/*
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* Cache strategies
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*/
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/* The NULL strategy leaves everything up to the controller. This tends to be a
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* pessimal but functional choice.
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*/
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#define CACHE_NULL 0
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/* Prefetch data when reading. We continually attempt to load the next 32 sectors
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* into the controller cache.
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*/
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#define CACHE_PREFETCH 1
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/* Prefetch data when reading. We sometimes attempt to load the next 32 sectors
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* into the controller cache. When an I/O is less <= 8K we assume its probably
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* not sequential and don't prefetch (default)
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*/
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#define CACHE_SMARTFETCH 2
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/* Data is written to the cache and then out on to the disk. The I/O must be
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* physically on the medium before the write is acknowledged (default without
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* NVRAM)
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*/
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#define CACHE_WRITETHROUGH 17
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/* Data is written to the cache and then out on to the disk. The controller
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* is permitted to write back the cache any way it wants. (default if battery
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* backed NVRAM is present). It can be useful to set this for swap regardless of
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* battery state.
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*/
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#define CACHE_WRITEBACK 18
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/* Optimise for under powered controllers, especially on RAID1 and RAID0. We
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* write large I/O's directly to disk bypassing the cache to avoid the extra
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* memory copy hits. Small writes are writeback cached
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*/
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#define CACHE_SMARTBACK 19
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/* Optimise for under powered controllers, especially on RAID1 and RAID0. We
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* write large I/O's directly to disk bypassing the cache to avoid the extra
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* memory copy hits. Small writes are writethrough cached. Suitable for devices
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* lacking battery backup
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*/
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#define CACHE_SMARTTHROUGH 20
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/*
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* Ioctl structures
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*/
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#define BLKI2OGRSTRAT _IOR('2', 1, int)
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#define BLKI2OGWSTRAT _IOR('2', 2, int)
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#define BLKI2OSRSTRAT _IOW('2', 3, int)
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#define BLKI2OSWSTRAT _IOW('2', 4, int)
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/*
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* I2O Function codes
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*/
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/*
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* Executive Class
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*/
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#define I2O_CMD_ADAPTER_ASSIGN 0xB3
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#define I2O_CMD_ADAPTER_READ 0xB2
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#define I2O_CMD_ADAPTER_RELEASE 0xB5
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#define I2O_CMD_BIOS_INFO_SET 0xA5
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#define I2O_CMD_BOOT_DEVICE_SET 0xA7
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#define I2O_CMD_CONFIG_VALIDATE 0xBB
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#define I2O_CMD_CONN_SETUP 0xCA
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#define I2O_CMD_DDM_DESTROY 0xB1
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#define I2O_CMD_DDM_ENABLE 0xD5
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#define I2O_CMD_DDM_QUIESCE 0xC7
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#define I2O_CMD_DDM_RESET 0xD9
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#define I2O_CMD_DDM_SUSPEND 0xAF
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#define I2O_CMD_DEVICE_ASSIGN 0xB7
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#define I2O_CMD_DEVICE_RELEASE 0xB9
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#define I2O_CMD_HRT_GET 0xA8
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#define I2O_CMD_ADAPTER_CLEAR 0xBE
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#define I2O_CMD_ADAPTER_CONNECT 0xC9
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#define I2O_CMD_ADAPTER_RESET 0xBD
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#define I2O_CMD_LCT_NOTIFY 0xA2
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#define I2O_CMD_OUTBOUND_INIT 0xA1
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#define I2O_CMD_PATH_ENABLE 0xD3
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#define I2O_CMD_PATH_QUIESCE 0xC5
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#define I2O_CMD_PATH_RESET 0xD7
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#define I2O_CMD_STATIC_MF_CREATE 0xDD
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#define I2O_CMD_STATIC_MF_RELEASE 0xDF
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#define I2O_CMD_STATUS_GET 0xA0
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#define I2O_CMD_SW_DOWNLOAD 0xA9
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#define I2O_CMD_SW_UPLOAD 0xAB
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#define I2O_CMD_SW_REMOVE 0xAD
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#define I2O_CMD_SYS_ENABLE 0xD1
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#define I2O_CMD_SYS_MODIFY 0xC1
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#define I2O_CMD_SYS_QUIESCE 0xC3
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#define I2O_CMD_SYS_TAB_SET 0xA3
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/*
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* Utility Class
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*/
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#define I2O_CMD_UTIL_NOP 0x00
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#define I2O_CMD_UTIL_ABORT 0x01
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#define I2O_CMD_UTIL_CLAIM 0x09
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#define I2O_CMD_UTIL_RELEASE 0x0B
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#define I2O_CMD_UTIL_PARAMS_GET 0x06
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#define I2O_CMD_UTIL_PARAMS_SET 0x05
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#define I2O_CMD_UTIL_EVT_REGISTER 0x13
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#define I2O_CMD_UTIL_EVT_ACK 0x14
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#define I2O_CMD_UTIL_CONFIG_DIALOG 0x10
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#define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D
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#define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F
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#define I2O_CMD_UTIL_LOCK 0x17
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#define I2O_CMD_UTIL_LOCK_RELEASE 0x19
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#define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15
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/*
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* SCSI Host Bus Adapter Class
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*/
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#define I2O_CMD_SCSI_EXEC 0x81
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#define I2O_CMD_SCSI_ABORT 0x83
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#define I2O_CMD_SCSI_BUSRESET 0x27
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/*
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* Random Block Storage Class
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*/
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#define I2O_CMD_BLOCK_READ 0x30
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#define I2O_CMD_BLOCK_WRITE 0x31
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#define I2O_CMD_BLOCK_CFLUSH 0x37
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#define I2O_CMD_BLOCK_MLOCK 0x49
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#define I2O_CMD_BLOCK_MUNLOCK 0x4B
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#define I2O_CMD_BLOCK_MMOUNT 0x41
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#define I2O_CMD_BLOCK_MEJECT 0x43
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#define I2O_CMD_BLOCK_POWER 0x70
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#define I2O_PRIVATE_MSG 0xFF
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/* Command status values */
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#define I2O_CMD_IN_PROGRESS 0x01
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#define I2O_CMD_REJECTED 0x02
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#define I2O_CMD_FAILED 0x03
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#define I2O_CMD_COMPLETED 0x04
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/* I2O API function return values */
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#define I2O_RTN_NO_ERROR 0
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#define I2O_RTN_NOT_INIT 1
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#define I2O_RTN_FREE_Q_EMPTY 2
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#define I2O_RTN_TCB_ERROR 3
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#define I2O_RTN_TRANSACTION_ERROR 4
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#define I2O_RTN_ADAPTER_ALREADY_INIT 5
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#define I2O_RTN_MALLOC_ERROR 6
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#define I2O_RTN_ADPTR_NOT_REGISTERED 7
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#define I2O_RTN_MSG_REPLY_TIMEOUT 8
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#define I2O_RTN_NO_STATUS 9
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#define I2O_RTN_NO_FIRM_VER 10
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#define I2O_RTN_NO_LINK_SPEED 11
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/* Reply message status defines for all messages */
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#define I2O_REPLY_STATUS_SUCCESS 0x00
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#define I2O_REPLY_STATUS_ABORT_DIRTY 0x01
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#define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02
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#define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03
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#define I2O_REPLY_STATUS_ERROR_DIRTY 0x04
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#define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05
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#define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06
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#define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08
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#define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09
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#define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A
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#define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B
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#define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80
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/* Status codes and Error Information for Parameter functions */
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#define I2O_PARAMS_STATUS_SUCCESS 0x00
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#define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01
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#define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02
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#define I2O_PARAMS_STATUS_BUFFER_FULL 0x03
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#define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04
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#define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05
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#define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06
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#define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07
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#define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08
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#define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09
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#define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A
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#define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B
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#define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C
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#define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D
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#define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E
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#define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F
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#define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10
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/* DetailedStatusCode defines for Executive, DDM, Util and Transaction error
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* messages: Table 3-2 Detailed Status Codes.*/
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#define I2O_DSC_SUCCESS 0x0000
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#define I2O_DSC_BAD_KEY 0x0002
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#define I2O_DSC_TCL_ERROR 0x0003
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#define I2O_DSC_REPLY_BUFFER_FULL 0x0004
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#define I2O_DSC_NO_SUCH_PAGE 0x0005
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#define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006
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#define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007
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#define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009
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#define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A
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#define I2O_DSC_DEVICE_LOCKED 0x000B
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#define I2O_DSC_DEVICE_RESET 0x000C
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#define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D
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#define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E
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#define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F
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#define I2O_DSC_INVALID_OFFSET 0x0010
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#define I2O_DSC_INVALID_PARAMETER 0x0011
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#define I2O_DSC_INVALID_REQUEST 0x0012
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#define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013
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#define I2O_DSC_MESSAGE_TOO_LARGE 0x0014
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#define I2O_DSC_MESSAGE_TOO_SMALL 0x0015
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#define I2O_DSC_MISSING_PARAMETER 0x0016
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#define I2O_DSC_TIMEOUT 0x0017
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#define I2O_DSC_UNKNOWN_ERROR 0x0018
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#define I2O_DSC_UNKNOWN_FUNCTION 0x0019
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#define I2O_DSC_UNSUPPORTED_VERSION 0x001A
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#define I2O_DSC_DEVICE_BUSY 0x001B
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#define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C
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|
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/* FailureStatusCodes, Table 3-3 Message Failure Codes */
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|
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#define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81
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|
#define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82
|
|
#define I2O_FSC_TRANSPORT_CONGESTION 0x83
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|
#define I2O_FSC_TRANSPORT_FAILURE 0x84
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|
#define I2O_FSC_TRANSPORT_STATE_ERROR 0x85
|
|
#define I2O_FSC_TRANSPORT_TIME_OUT 0x86
|
|
#define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87
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|
#define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88
|
|
#define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89
|
|
#define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A
|
|
#define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B
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|
#define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C
|
|
#define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D
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|
#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E
|
|
#define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F
|
|
#define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF
|
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|
|
/* Device Claim Types */
|
|
#define I2O_CLAIM_PRIMARY 0x01000000
|
|
#define I2O_CLAIM_MANAGEMENT 0x02000000
|
|
#define I2O_CLAIM_AUTHORIZED 0x03000000
|
|
#define I2O_CLAIM_SECONDARY 0x04000000
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|
|
|
/* Message header defines for VersionOffset */
|
|
#define I2OVER15 0x0001
|
|
#define I2OVER20 0x0002
|
|
|
|
/* Default is 1.5, FIXME: Need support for both 1.5 and 2.0 */
|
|
#define I2OVERSION I2OVER15
|
|
|
|
#define SGL_OFFSET_0 I2OVERSION
|
|
#define SGL_OFFSET_4 (0x0040 | I2OVERSION)
|
|
#define SGL_OFFSET_5 (0x0050 | I2OVERSION)
|
|
#define SGL_OFFSET_6 (0x0060 | I2OVERSION)
|
|
#define SGL_OFFSET_7 (0x0070 | I2OVERSION)
|
|
#define SGL_OFFSET_8 (0x0080 | I2OVERSION)
|
|
#define SGL_OFFSET_9 (0x0090 | I2OVERSION)
|
|
#define SGL_OFFSET_10 (0x00A0 | I2OVERSION)
|
|
|
|
#define TRL_OFFSET_5 (0x0050 | I2OVERSION)
|
|
#define TRL_OFFSET_6 (0x0060 | I2OVERSION)
|
|
|
|
/* Transaction Reply Lists (TRL) Control Word structure */
|
|
#define TRL_SINGLE_FIXED_LENGTH 0x00
|
|
#define TRL_SINGLE_VARIABLE_LENGTH 0x40
|
|
#define TRL_MULTIPLE_FIXED_LENGTH 0x80
|
|
|
|
|
|
/* msg header defines for MsgFlags */
|
|
#define MSG_STATIC 0x0100
|
|
#define MSG_64BIT_CNTXT 0x0200
|
|
#define MSG_MULTI_TRANS 0x1000
|
|
#define MSG_FAIL 0x2000
|
|
#define MSG_FINAL 0x4000
|
|
#define MSG_REPLY 0x8000
|
|
|
|
/* minimum size msg */
|
|
#define THREE_WORD_MSG_SIZE 0x00030000
|
|
#define FOUR_WORD_MSG_SIZE 0x00040000
|
|
#define FIVE_WORD_MSG_SIZE 0x00050000
|
|
#define SIX_WORD_MSG_SIZE 0x00060000
|
|
#define SEVEN_WORD_MSG_SIZE 0x00070000
|
|
#define EIGHT_WORD_MSG_SIZE 0x00080000
|
|
#define NINE_WORD_MSG_SIZE 0x00090000
|
|
#define TEN_WORD_MSG_SIZE 0x000A0000
|
|
#define ELEVEN_WORD_MSG_SIZE 0x000B0000
|
|
#define I2O_MESSAGE_SIZE(x) ((x)<<16)
|
|
|
|
|
|
/* Special TID Assignments */
|
|
|
|
#define ADAPTER_TID 0
|
|
#define HOST_TID 1
|
|
|
|
#define MSG_FRAME_SIZE 64 /* i2o_scsi assumes >= 32 */
|
|
#define NMBR_MSG_FRAMES 128
|
|
|
|
#define MSG_POOL_SIZE (MSG_FRAME_SIZE*NMBR_MSG_FRAMES*sizeof(u32))
|
|
|
|
#define I2O_POST_WAIT_OK 0
|
|
#define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT
|
|
|
|
#endif /* __KERNEL__ */
|
|
#endif /* _I2O_H */
|