322 lines
9.7 KiB
C
322 lines
9.7 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 Waldorf GMBH
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* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
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* Copyright (C) 1996 Paul M. Antoine
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_PROCESSOR_H
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#define _ASM_PROCESSOR_H
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#include <linux/config.h>
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#include <linux/cache.h>
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#include <asm/isadep.h>
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/*
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* Return current * instruction pointer ("program counter").
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*/
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#define current_text_addr() ({ __label__ _l; _l: &&_l;})
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#ifndef __ASSEMBLY__
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#include <linux/smp.h>
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#include <linux/threads.h>
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#include <asm/cachectl.h>
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#include <asm/cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/reg.h>
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#include <asm/system.h>
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/*
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* Descriptor for a cache
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*/
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struct cache_desc {
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unsigned short linesz; /* Size of line in bytes */
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unsigned short ways; /* Number of ways */
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unsigned short sets; /* Number of lines per set */
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unsigned int waysize; /* Bytes per way */
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unsigned int waybit; /* Bits to select in a cache set */
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unsigned int flags; /* Flags describing cache properties */
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};
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/*
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* Flag definitions
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*/
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#define MIPS_CACHE_NOT_PRESENT 0x00000001
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#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
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#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
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#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
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struct cpuinfo_mips {
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unsigned long udelay_val;
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unsigned long *pgd_quick;
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unsigned long *pte_quick;
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unsigned long pgtable_cache_sz;
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unsigned long asid_cache;
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/*
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* Capability and feature descriptor structure for MIPS CPU
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*/
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unsigned long options;
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unsigned int processor_id;
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unsigned int fpu_id;
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unsigned int cputype;
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int isa_level;
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int tlbsize;
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struct cache_desc icache; /* Primary I-cache */
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struct cache_desc dcache; /* Primary D or combined I/D cache */
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struct cache_desc scache; /* Secondary cache */
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struct cache_desc tcache; /* Tertiary/split secondary cache */
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} __attribute__((aligned(SMP_CACHE_BYTES)));
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/*
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* Assumption: Options of CPU 0 are a superset of all processors.
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* This is true for all known MIPS systems.
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*/
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#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
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#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
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#define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB)
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#define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
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#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
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#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
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#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
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#define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16)
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#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
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#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
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#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
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#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
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#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
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#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
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#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
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#define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
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#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
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#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
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#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
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#define cpu_has_ic_fills_f_dc (cpu_data[0].dcache.flags & MIPS_CACHE_IC_F_DC)
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#define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
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#define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
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#define cpu_has_64bit_gp_regs 0
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#define cpu_has_64bit_addresses 0
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#define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
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#define cpu_dcache_line_size() current_cpu_data.dcache.linesz
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#define cpu_icache_line_size() current_cpu_data.icache.linesz
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#define cpu_scache_line_size() current_cpu_data.scache.linesz
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extern struct cpuinfo_mips cpu_data[];
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#define current_cpu_data cpu_data[smp_processor_id()]
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extern void cpu_probe(void);
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extern void cpu_report(void);
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/*
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* System setup and hardware flags..
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*/
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extern void (*cpu_wait)(void);
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extern unsigned int vced_count, vcei_count;
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/*
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* Bus types (default is ISA, but people can check others with these..)
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*/
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#ifdef CONFIG_EISA
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extern int EISA_bus;
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#else
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#define EISA_bus (0)
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#endif
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#define MCA_bus 0
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#define MCA_bus__is_a_macro /* for versions in ksyms.c */
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/*
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* User space process size: 2GB. This is hardcoded into a few places,
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* so don't change it unless you know what you are doing. TASK_SIZE
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* for a 64 bit kernel expandable to 8192EB, of which the current MIPS
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* implementations will "only" be able to use 1TB ...
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*/
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#define TASK_SIZE 0x7fff8000UL
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/* This decides where the kernel will search for a free chunk of vm
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* space during mmap's.
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*/
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#define TASK_UNMAPPED_BASE (TASK_SIZE / 3)
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/*
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* Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
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*/
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#define IO_BITMAP_SIZE 32
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#define NUM_FPU_REGS 32
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struct mips_fpu_hard_struct {
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double fp_regs[NUM_FPU_REGS];
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unsigned int control;
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};
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/*
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* It would be nice to add some more fields for emulator statistics, but there
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* are a number of fixed offsets in offset.h and elsewhere that would have to
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* be recalculated by hand. So the additional information will be private to
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* the FPU emulator for now. See asm-mips/fpu_emulator.h.
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*/
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typedef u64 fpureg_t;
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struct mips_fpu_soft_struct {
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fpureg_t regs[NUM_FPU_REGS];
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unsigned int sr;
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};
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union mips_fpu_union {
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struct mips_fpu_hard_struct hard;
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struct mips_fpu_soft_struct soft;
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};
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#define INIT_FPU { \
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{{0,},} \
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}
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typedef struct {
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unsigned long seg;
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} mm_segment_t;
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/*
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* If you change thread_struct remember to change the #defines below too!
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*/
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struct thread_struct {
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/* Saved main processor registers. */
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unsigned long reg16;
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unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
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unsigned long reg29, reg30, reg31;
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/* Saved cp0 stuff. */
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unsigned long cp0_status;
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/* Saved fpu/fpu emulator stuff. */
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union mips_fpu_union fpu;
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/* Other stuff associated with the thread. */
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unsigned long cp0_badvaddr; /* Last user fault */
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unsigned long cp0_baduaddr; /* Last kernel fault accessing USEG */
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unsigned long error_code;
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unsigned long trap_no;
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#define MF_FIXADE 1 /* Fix address errors in software */
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#define MF_LOGADE 2 /* Log address errors to syslog */
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unsigned long mflags;
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mm_segment_t current_ds;
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unsigned long irix_trampoline; /* Wheee... */
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unsigned long irix_oldctx;
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};
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#endif /* !__ASSEMBLY__ */
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#define INIT_THREAD { \
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/* \
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* saved main processor registers \
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*/ \
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0, 0, 0, 0, 0, 0, 0, 0, \
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0, 0, 0, \
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/* \
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* saved cp0 stuff \
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*/ \
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0, \
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/* \
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* saved fpu/fpu emulator stuff \
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*/ \
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INIT_FPU, \
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/* \
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* Other stuff associated with the process \
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*/ \
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0, 0, 0, 0, \
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/* \
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* For now the default is to fix address errors \
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*/ \
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MF_FIXADE, { 0 }, 0, 0 \
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}
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#ifdef __KERNEL__
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#define KERNEL_STACK_SIZE 0x2000
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#ifndef __ASSEMBLY__
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/* Free all resources held by a thread. */
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#define release_thread(thread) do { } while(0)
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extern int arch_kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
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/* Copy and release all segment info associated with a VM */
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#define copy_segments(p, mm) do { } while(0)
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#define release_segments(mm) do { } while(0)
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struct mips_frame_info {
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int frame_offset;
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int pc_offset;
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};
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extern struct mips_frame_info schedule_frame;
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/*
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* Return saved PC of a blocked thread.
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*/
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static inline unsigned long thread_saved_pc(struct thread_struct *t)
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{
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extern void ret_from_fork(void);
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/* New born processes are a special case */
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if (t->reg31 == (unsigned long) ret_from_fork)
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return t->reg31;
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if (schedule_frame.pc_offset < 0)
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return 0;
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return ((unsigned long *)t->reg29)[schedule_frame.pc_offset];
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}
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/*
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* Do necessary setup to start up a newly executed thread.
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*/
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extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
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struct task_struct;
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unsigned long get_wchan(struct task_struct *p);
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#define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs))
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#define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - 32)
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#define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc)))
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#define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29])))
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#define KSTK_STATUS(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_status)))
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/* Allocation and freeing of basic task resources. */
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/*
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* NOTE! The task struct and the stack go together
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*/
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#define THREAD_ORDER (PAGE_SHIFT >= 14 ? 0 : 1)
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#define THREAD_SIZE (PAGE_SIZE << THREAD_ORDER)
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#define THREAD_MASK (THREAD_SIZE - 1UL)
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#define alloc_task_struct() \
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((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
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#define free_task_struct(p) free_pages((unsigned long)(p),1)
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#define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
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#define init_task (init_task_union.task)
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#define init_stack (init_task_union.stack)
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#define cpu_relax() barrier()
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#endif /* !__ASSEMBLY__ */
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#endif /* __KERNEL__ */
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/*
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* Return_address is a replacement for __builtin_return_address(count)
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* which on certain architectures cannot reasonably be implemented in GCC
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* (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
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* Note that __builtin_return_address(x>=1) is forbidden because GCC
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* aborts compilation on some CPUs. It's simply not possible to unwind
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* some CPU's stackframes.
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*
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* __builtin_return_address works only for non-leaf functions. We avoid the
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* overhead of a function call by forcing the compiler to save the return
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* address register on the stack.
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*/
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#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
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#endif /* _ASM_PROCESSOR_H */
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