317 lines
9.5 KiB
C
317 lines
9.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle at alii
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* Copyright (C) 1999 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_PGTABLE_H
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#define _ASM_PGTABLE_H
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#include <linux/config.h>
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#include <asm/addrspace.h>
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#include <asm/page.h>
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#ifndef _LANGUAGE_ASSEMBLY
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#include <linux/linkage.h>
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#include <asm/cachectl.h>
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#include <asm/cacheflush.h>
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#include <asm/fixmap.h>
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#include <asm/types.h>
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/*
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* This flag is used to indicate that the page pointed to by a pte
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* is dirty and requires cleaning before returning it to the user.
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*/
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#define PG_dcache_dirty PG_arch_1
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#define Page_dcache_dirty(page) \
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test_bit(PG_dcache_dirty, &(page)->flags)
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#define SetPageDcacheDirty(page) \
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set_bit(PG_dcache_dirty, &(page)->flags)
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#define ClearPageDcacheDirty(page) \
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clear_bit(PG_dcache_dirty, &(page)->flags)
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/*
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* - add_wired_entry() add a fixed TLB entry, and move wired register
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*/
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extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long entryhi, unsigned long pagemask);
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/*
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* - add_temporary_entry() add a temporary TLB entry. We use TLB entries
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* starting at the top and working down. This is for populating the
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* TLB before trap_init() puts the TLB miss handler in place. It
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* should be used only for entries matching the actual page tables,
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* to prevent inconsistencies.
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*/
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extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
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unsigned long entryhi, unsigned long pagemask);
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/* Basically we have the same two-level (which is the logical three level
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* Linux page table layout folded) page tables as the i386. Some day
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* when we have proper page coloring support we can have a 1% quicker
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* tlb refill handling mechanism, but for now it is a bit slower but
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* works even with the cache aliasing problem the R4k and above have.
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*/
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/* PMD_SHIFT determines the size of the area a second-level page table can map */
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#ifdef CONFIG_64BIT_PHYS_ADDR
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extern int remap_page_range_high(unsigned long from, phys_t to, unsigned long size, pgprot_t prot);
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#endif
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#endif /* !defined (_LANGUAGE_ASSEMBLY) */
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#define PMD_SIZE (1UL << PMD_SHIFT)
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#define PMD_MASK (~(PMD_SIZE-1))
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define PGDIR_SHIFT PMD_SHIFT
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
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#define FIRST_USER_PGD_NR 0
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#define VMALLOC_START KSEG2
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#define VMALLOC_VMADDR(x) ((unsigned long)(x))
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#if CONFIG_HIGHMEM
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# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
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#else
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# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
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#endif
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#include <asm/pgtable-bits.h>
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#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
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#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
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PAGE_CACHABLE_DEFAULT)
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#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
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PAGE_CACHABLE_DEFAULT)
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#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
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PAGE_CACHABLE_DEFAULT)
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#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
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_PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT)
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#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
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PAGE_CACHABLE_DEFAULT)
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#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
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__WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
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/*
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* MIPS can't do page protection for execute, and considers that the same like
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* read. Also, write permissions imply read permissions. This is the closest
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* we can get by reasonable means..
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*/
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READONLY
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#define __P010 PAGE_COPY
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#define __P011 PAGE_COPY
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#define __P100 PAGE_READONLY
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#define __P101 PAGE_READONLY
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#define __P110 PAGE_COPY
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#define __P111 PAGE_COPY
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READONLY
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#define __S010 PAGE_SHARED
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#define __S011 PAGE_SHARED
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#define __S100 PAGE_READONLY
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#define __S101 PAGE_READONLY
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#define __S110 PAGE_SHARED
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#define __S111 PAGE_SHARED
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#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
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#include <asm/pgtable-64.h>
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#else
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#include <asm/pgtable-32.h>
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#endif
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#if !defined (_LANGUAGE_ASSEMBLY)
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extern unsigned long empty_zero_page;
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extern unsigned long zero_page_mask;
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#define ZERO_PAGE(vaddr) \
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(virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask)))
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extern void load_pgd(unsigned long pg_dir);
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extern pmd_t invalid_pte_table[PAGE_SIZE/sizeof(pmd_t)];
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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static inline unsigned long pmd_page(pmd_t pmd)
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{
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return pmd_val(pmd);
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}
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static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
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{
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pmd_val(*pmdp) = (((unsigned long) ptep) & PAGE_MASK);
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}
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static inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; }
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/*
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* (pmds are folded into pgds so this doesn't get actually called,
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* but the define is needed for a generic inline function.)
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*/
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#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
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#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
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/*
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* Empty pgd/pmd entries point to the invalid_pte_table.
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*/
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static inline int pmd_none(pmd_t pmd)
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{
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return pmd_val(pmd) == (unsigned long) invalid_pte_table;
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}
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static inline int pmd_bad(pmd_t pmd)
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{
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return ((pmd_page(pmd) > (unsigned long) high_memory) ||
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(pmd_page(pmd) < PAGE_OFFSET));
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}
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static inline int pmd_present(pmd_t pmd)
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{
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return (pmd_val(pmd) != (unsigned long) invalid_pte_table);
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}
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static inline void pmd_clear(pmd_t *pmdp)
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{
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pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
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}
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/*
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* The "pgd_xxx()" functions here are trivial for a folded two-level
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* setup: the pgd is never bad, and a pmd always exists (as it's folded
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* into the pgd entry)
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*/
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static inline int pgd_none(pgd_t pgd) { return 0; }
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static inline int pgd_bad(pgd_t pgd) { return 0; }
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static inline int pgd_present(pgd_t pgd) { return 1; }
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static inline void pgd_clear(pgd_t *pgdp) { }
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_READ; }
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static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_WRITE; }
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static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_MODIFIED; }
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static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; }
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/*
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* (pmds are folded into pgds so this doesnt get actually called,
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* but the define is needed for a generic inline function.)
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*/
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#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
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#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
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#define PGD_T_LOG2 ffz(~sizeof(pgd_t))
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#define PMD_T_LOG2 ffz(~sizeof(pmd_t))
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#define PTE_T_LOG2 ffz(~sizeof(pte_t))
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#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
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#define PTRS_PER_PMD 1
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#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
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#define page_pte(page) page_pte_prot(page, __pgprot(0))
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#define __pgd_offset(address) pgd_index(address)
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#define __pmd_offset(address) \
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(((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
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/* to find an entry in a kernel page-table-directory */
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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#define pgd_index(address) ((address) >> PGDIR_SHIFT)
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/* to find an entry in a page-table-directory */
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static inline pgd_t *pgd_offset(struct mm_struct *mm, unsigned long address)
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{
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return mm->pgd + pgd_index(address);
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}
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/* Find an entry in the second-level page table.. */
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static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
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{
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return (pmd_t *) dir;
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}
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/* Find an entry in the third-level page table.. */
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static inline pte_t *pte_offset(pmd_t * dir, unsigned long address)
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{
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return (pte_t *) (pmd_page(*dir)) +
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((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
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}
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extern int do_check_pgt_cache(int, int);
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extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
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extern void paging_init(void);
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extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
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pte_t pte);
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extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
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pte_t pte);
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static inline void update_mmu_cache(struct vm_area_struct *vma,
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unsigned long address, pte_t pte)
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{
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__update_tlb(vma, address, pte);
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__update_cache(vma, address, pte);
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}
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/* Swap entries must have VALID and GLOBAL bits cleared. */
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#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
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#define SWP_TYPE(x) (((x).val >> 1) & 0x7f)
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#define SWP_OFFSET(x) ((x).val >> 10)
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#define SWP_ENTRY(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 10) })
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#else
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#define SWP_TYPE(x) (((x).val >> 1) & 0x1f)
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#define SWP_OFFSET(x) ((x).val >> 8)
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#define SWP_ENTRY(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
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#endif
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#define pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_low })
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#define swp_entry_to_pte(x) ((pte_t) { (x).val })
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/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
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#define PageSkip(page) (0)
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#define kern_addr_valid(addr) (1)
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#include <asm-generic/pgtable.h>
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#endif /* !defined (_LANGUAGE_ASSEMBLY) */
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/*
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* We provide our own get_unmapped area to cope with the virtual aliasing
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* constraints placed on us by the cache architecture.
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*/
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#define HAVE_ARCH_UNMAPPED_AREA
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#ifdef CONFIG_64BIT_PHYS_ADDR
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#define io_remap_page_range remap_page_range_high
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#else
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#define io_remap_page_range remap_page_range
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#endif
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/*
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* No page table caches to initialise
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*/
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#define pgtable_cache_init() do { } while (0)
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#endif /* _ASM_PGTABLE_H */
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