490 lines
15 KiB
C
490 lines
15 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 1995 Waldorf GmbH
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* Copyright (C) 1994 - 2000 Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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* Copyright (C) 2000 FSMLabs, Inc.
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*/
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#ifndef _ASM_IO_H
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#define _ASM_IO_H
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#include <linux/config.h>
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#include <linux/pagemap.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/pgtable-bits.h>
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#include <asm/byteorder.h>
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#ifdef CONFIG_SGI_IP27
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extern unsigned long bus_to_baddr[256];
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#define bus_to_baddr(bus, addr) (bus_to_baddr[(bus)->number] + (addr))
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#define baddr_to_bus(bus, addr) ((addr) - bus_to_baddr[(bus)->number])
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#define __swizzle_addr_w(port) ((port) ^ 2)
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#else
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#define bus_to_baddr(bus, addr) (addr)
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#define baddr_to_bus(bus, addr) (addr)
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#define __swizzle_addr_w(port) (port)
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#endif
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/*
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* Slowdown I/O port space accesses for antique hardware.
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*/
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#undef CONF_SLOWDOWN_IO
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/*
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* Sane hardware offers swapping of I/O space accesses in hardware; less
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* sane hardware forces software to fiddle with this. Totally insane hardware
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* introduces special cases like:
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*
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* IP22 seems braindead enough to swap 16-bits values in hardware, but not
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* 32-bits. Go figure... Can't tell without documentation.
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*
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* We only do the swapping to keep the kernel config bits of bi-endian
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* machines a bit saner.
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*/
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#if defined(CONFIG_SWAP_IO_SPACE_W) && defined(__MIPSEB__)
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#define __ioswab16(x) swab16(x)
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#else
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#define __ioswab16(x) (x)
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#endif
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#if defined(CONFIG_SWAP_IO_SPACE_L) && defined(__MIPSEB__)
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#define __ioswab32(x) swab32(x)
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#else
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#define __ioswab32(x) (x)
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#endif
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/*
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* Change "struct page" to physical address.
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*/
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#ifdef CONFIG_64BIT_PHYS_ADDR
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#define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
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#else
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#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
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#endif
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#define IO_SPACE_LIMIT 0xffff
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extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags);
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/*
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* ioremap - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*/
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#define ioremap(offset, size) \
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__ioremap((offset), (size), _CACHE_UNCACHED)
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/*
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* ioremap_nocache - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap_nocache performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* This version of ioremap ensures that the memory is marked uncachable
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* on the CPU as well as honouring existing caching rules from things like
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* the PCI bus. Note that there are other caches and buffers on many
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* busses. In paticular driver authors should read up on PCI writes
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*
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* It's useful if some control registers are in such an area and
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* write combining or read caching is not desirable:
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*/
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#define ioremap_nocache(offset, size) \
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__ioremap((offset), (size), _CACHE_UNCACHED)
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#define ioremap_cacheable_cow(offset, size) \
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__ioremap((offset), (size), _CACHE_CACHABLE_COW)
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#define ioremap_uncached_accelerated(offset, size) \
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__ioremap((offset), (size), _CACHE_UNCACHED_ACCELERATED)
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extern void iounmap(void *addr);
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/*
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* XXX We need system specific versions of these to handle EISA address bits
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* 24-31 on SNI.
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* XXX more SNI hacks.
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*/
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#define readb(addr) (*(volatile unsigned char *)(addr))
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#define readw(addr) __ioswab16((*(volatile unsigned short *)(addr)))
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#define readl(addr) __ioswab32((*(volatile unsigned int *)(addr)))
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#define __raw_readb(addr) (*(volatile unsigned char *)(addr))
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#define __raw_readw(addr) (*(volatile unsigned short *)(addr))
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#define __raw_readl(addr) (*(volatile unsigned int *)(addr))
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#define writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (b))
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#define writew(b,addr) ((*(volatile unsigned short *)(addr)) = (__ioswab16(b)))
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#define writel(b,addr) ((*(volatile unsigned int *)(addr)) = (__ioswab32(b)))
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#define __raw_writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (b))
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#define __raw_writew(w,addr) ((*(volatile unsigned short *)(addr)) = (w))
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#define __raw_writel(l,addr) ((*(volatile unsigned int *)(addr)) = (l))
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/*
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* TODO: Should use variants that don't do prefetching.
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*/
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#define memset_io(a,b,c) memset((void *)(a),(b),(c))
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#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
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#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
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/*
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* isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
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* for the processor. This implies the assumption that there is only
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* one of these busses.
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*/
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extern unsigned long isa_slot_offset;
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/*
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* ISA space is 'always mapped' on currently supported MIPS systems, no need
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* to explicitly ioremap() it. The fact that the ISA IO space is mapped
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* to PAGE_OFFSET is pure coincidence - it does not mean ISA values
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* are physical addresses. The following constant pointer can be
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* used as the IO-area pointer (it can be iounmapped as well, so the
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* analogy with PCI is quite large):
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*/
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#define __ISA_IO_base ((char *)(isa_slot_offset))
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#define isa_readb(a) readb(__ISA_IO_base + (a))
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#define isa_readw(a) readw(__ISA_IO_base + (a))
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#define isa_readl(a) readl(__ISA_IO_base + (a))
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#define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
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#define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
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#define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
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#define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c))
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#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
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#define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c))
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/*
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* We don't have csum_partial_copy_fromio() yet, so we cheat here and
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* just copy it. The net code will then do the checksum later.
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*/
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#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
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#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
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/*
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* check_signature - find BIOS signatures
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* @io_addr: mmio address to check
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* @signature: signature block
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* @length: length of signature
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*
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* Perform a signature comparison with the mmio address io_addr. This
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* address should have been obtained by ioremap.
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* Returns 1 on a match.
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*/
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static inline int check_signature(unsigned long io_addr,
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const unsigned char *signature, int length)
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{
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int retval = 0;
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do {
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if (readb(io_addr) != *signature)
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goto out;
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io_addr++;
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signature++;
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length--;
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} while (length);
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retval = 1;
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out:
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return retval;
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}
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/*
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* isa_check_signature - find BIOS signatures
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* @io_addr: mmio address to check
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* @signature: signature block
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* @length: length of signature
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*
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* Perform a signature comparison with the ISA mmio address io_addr.
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* Returns 1 on a match.
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*
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* This function is deprecated. New drivers should use ioremap and
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* check_signature.
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*/
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static inline int isa_check_signature(unsigned long io_addr,
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const unsigned char *signature, int length)
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{
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int retval = 0;
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do {
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if (isa_readb(io_addr) != *signature)
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goto out;
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io_addr++;
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signature++;
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length--;
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} while (length);
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retval = 1;
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out:
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return retval;
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}
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/*
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* virt_to_phys - map virtual addresses to physical
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* @address: address to remap
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*
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* The returned physical address is the physical (CPU) mapping for
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* the memory address given. It is only valid to use this function on
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* addresses directly mapped or allocated via kmalloc.
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*
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* This function does not give bus mappings for DMA transfers. In
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* almost all conceivable cases a device driver should not be using
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* this function
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*/
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static inline unsigned long virt_to_phys(volatile void * address)
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{
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return (unsigned long)address - PAGE_OFFSET;
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}
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/*
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* phys_to_virt - map physical address to virtual
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* @address: address to remap
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*
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* The returned virtual address is a current CPU mapping for
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* the memory address given. It is only valid to use this function on
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* addresses that have a kernel mapping
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*
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* This function does not handle bus mappings for DMA transfers. In
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* almost all conceivable cases a device driver should not be using
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* this function
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*/
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static inline void * phys_to_virt(unsigned long address)
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{
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return (void *)(address + PAGE_OFFSET);
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}
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/*
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* IO bus memory addresses are also 1:1 with the physical address
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*/
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static inline unsigned long virt_to_bus(volatile void * address)
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{
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return (unsigned long)address - PAGE_OFFSET;
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}
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static inline void * bus_to_virt(unsigned long address)
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{
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return (void *)(address + PAGE_OFFSET);
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}
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/* This is too simpleminded for more sophisticated than dumb hardware ... */
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#define page_to_bus page_to_phys
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/*
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* On MIPS I/O ports are memory mapped, so we access them using normal
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* load/store instructions. mips_io_port_base is the virtual address to
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* which all ports are being mapped. For sake of efficiency some code
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* assumes that this is an address that can be loaded with a single lui
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* instruction, so the lower 16 bits must be zero. Should be true on
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* on any sane architecture; generic code does not use this assumption.
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*/
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extern const unsigned long mips_io_port_base;
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#define set_io_port_base(base) \
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do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
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#define __SLOW_DOWN_IO \
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__asm__ __volatile__( \
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"sb\t$0,0x80(%0)" \
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: : "r" (mips_io_port_base));
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#ifdef CONF_SLOWDOWN_IO
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#ifdef REALLY_SLOW_IO
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#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
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#else
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#define SLOW_DOWN_IO __SLOW_DOWN_IO
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#endif
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#else
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#define SLOW_DOWN_IO
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#endif
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#define outb(val,port) \
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do { \
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*(volatile u8 *)(mips_io_port_base + (port)) = (val); \
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} while(0)
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#define outw(val,port) \
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do { \
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*(volatile u16 *)(mips_io_port_base + __swizzle_addr_w(port)) = \
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__ioswab16(val); \
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} while(0)
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#define outl(val,port) \
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do { \
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*(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\
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} while(0)
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#define outb_p(val,port) \
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do { \
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*(volatile u8 *)(mips_io_port_base + (port)) = (val); \
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SLOW_DOWN_IO; \
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} while(0)
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#define outw_p(val,port) \
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do { \
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*(volatile u16 *)(mips_io_port_base + __swizzle_addr_w(port)) = \
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__ioswab16(val); \
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SLOW_DOWN_IO; \
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} while(0)
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#define outl_p(val,port) \
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do { \
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*(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\
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SLOW_DOWN_IO; \
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} while(0)
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static inline unsigned char inb(unsigned long port)
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{
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return *(volatile u8 *)(mips_io_port_base + port);
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}
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static inline unsigned short inw(unsigned long port)
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{
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port = __swizzle_addr_w(port);
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return __ioswab16(*(volatile u16 *)(mips_io_port_base + port));
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}
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static inline unsigned int inl(unsigned long port)
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{
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return __ioswab32(*(volatile u32 *)(mips_io_port_base + port));
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}
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static inline unsigned char inb_p(unsigned long port)
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{
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u8 __val;
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__val = *(volatile u8 *)(mips_io_port_base + port);
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SLOW_DOWN_IO;
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return __val;
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}
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static inline unsigned short inw_p(unsigned long port)
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{
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u16 __val;
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port = __swizzle_addr_w(port);
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__val = *(volatile u16 *)(mips_io_port_base + port);
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SLOW_DOWN_IO;
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return __ioswab16(__val);
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}
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static inline unsigned int inl_p(unsigned long port)
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{
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u32 __val;
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__val = *(volatile u32 *)(mips_io_port_base + port);
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SLOW_DOWN_IO;
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return __ioswab32(__val);
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}
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static inline void __outsb(unsigned long port, void *addr, unsigned int count)
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{
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while (count--) {
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outb(*(u8 *)addr, port);
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addr++;
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}
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}
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static inline void __insb(unsigned long port, void *addr, unsigned int count)
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{
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while (count--) {
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*(u8 *)addr = inb(port);
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addr++;
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}
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}
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static inline void __outsw(unsigned long port, void *addr, unsigned int count)
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{
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while (count--) {
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outw(*(u16 *)addr, port);
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addr += 2;
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}
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}
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static inline void __insw(unsigned long port, void *addr, unsigned int count)
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{
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while (count--) {
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*(u16 *)addr = inw(port);
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addr += 2;
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}
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}
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static inline void __outsl(unsigned long port, void *addr, unsigned int count)
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{
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while (count--) {
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outl(*(u32 *)addr, port);
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addr += 4;
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}
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}
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static inline void __insl(unsigned long port, void *addr, unsigned int count)
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{
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while (count--) {
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*(u32 *)addr = inl(port);
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addr += 4;
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}
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}
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#define outsb(port, addr, count) __outsb(port, addr, count)
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#define insb(port, addr, count) __insb(port, addr, count)
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#define outsw(port, addr, count) __outsw(port, addr, count)
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#define insw(port, addr, count) __insw(port, addr, count)
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#define outsl(port, addr, count) __outsl(port, addr, count)
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#define insl(port, addr, count) __insl(port, addr, count)
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/*
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* The caches on some architectures aren't dma-coherent and have need to
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* handle this in software. There are three types of operations that
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* can be applied to dma buffers.
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*
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* - dma_cache_wback_inv(start, size) makes caches and coherent by
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* writing the content of the caches back to memory, if necessary.
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* The function also invalidates the affected part of the caches as
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* necessary before DMA transfers from outside to memory.
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* - dma_cache_wback(start, size) makes caches and coherent by
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* writing the content of the caches back to memory, if necessary.
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* The function also invalidates the affected part of the caches as
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* necessary before DMA transfers from outside to memory.
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* - dma_cache_inv(start, size) invalidates the affected parts of the
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* caches. Dirty lines of the caches may be written back or simply
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* be discarded. This operation is necessary before dma operations
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* to the memory.
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*/
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#ifdef CONFIG_NONCOHERENT_IO
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extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
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extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
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extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
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#define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size)
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#define dma_cache_wback(start,size) _dma_cache_wback(start,size)
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#define dma_cache_inv(start,size) _dma_cache_inv(start,size)
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#else /* Sane hardware */
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#define dma_cache_wback_inv(start,size) \
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do { (void) (start); (void) (size); } while (0)
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#define dma_cache_wback(start,size) \
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do { (void) (start); (void) (size); } while (0)
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#define dma_cache_inv(start,size) \
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do { (void) (start); (void) (size); } while (0)
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#endif /* CONFIG_NONCOHERENT_IO */
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#endif /* _ASM_IO_H */
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