diff -uNr old/agg-rx.c new/agg-rx.c --- old/agg-rx.c 2022-12-10 20:11:05.000000000 +0800 +++ new/agg-rx.c 2023-05-05 19:26:48.197085000 +0800 @@ -174,6 +174,17 @@ return; tid = rcu_dereference(wcid->aggr[tidno]); +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + if(npu_enable()) + { + if(tid) + return; + } + else{ + if (!tid) + return; + } +#endif if (!tid) return; diff -uNr old/dma.c new/dma.c --- old/dma.c 2023-05-08 12:34:37.420918000 +0800 +++ new/dma.c 2023-05-08 11:05:14.154289000 +0800 @@ -6,6 +6,45 @@ #include #include "mt76.h" #include "dma.h" +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD +#include "mt76_npu_offload.h" +extern struct sk_buff *(*fromHostadptPktHandle_hook)(unsigned int ringIdx, unsigned char* preschedule); +extern void (*hostdapt_enable_int_hook)(unsigned int ringIdx); +extern void (*hostdapt_disable_int_hook)(unsigned int ringIdx); +extern void (*hostdapt_registe_wifitask_hook)(unsigned int ringIdx, void *func); +#endif + +#ifdef CONFIG_SOC_WOE +#include "mt7915/regs.h" +#include "mt76_woe.h" + +void +writel_mt76(unsigned int value, void *addr,struct mt76_queue *q){ + writel(value, addr); +} +int +readl_mt76(void *addr, struct mt76_queue *q){ + return readl(addr); +} + +struct woe_need pAd = { + .writel_api = writel_mt76, + .readl_api = readl_mt76, + .regs_phy0 = NULL, + .regs_phy1 = NULL, + .wed_running = 0, +}; +struct woe_need pAd_1 = { + .writel_api = writel_mt76, + .readl_api = readl_mt76, + .regs_phy0 = NULL, + .regs_phy1 = NULL, + .wed_running = 0, +}; +EXPORT_SYMBOL(pAd); +EXPORT_SYMBOL(pAd_1); +#endif + #if IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) @@ -209,6 +248,68 @@ static int mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q, struct mt76_queue_buf *buf, int nbufs, u32 info, + struct sk_buff *skb, void *txwi) +{ + struct mt76_queue_entry *entry; + struct mt76_desc *desc; + u32 ctrl; + int i, idx = -1; + + if (txwi) { + q->entry[q->head].txwi = DMA_DUMMY_DATA; + q->entry[q->head].skip_buf0 = true; + } + + for (i = 0; i < nbufs; i += 2, buf += 2) { + u32 buf0 = buf[0].addr, buf1 = 0; + + idx = q->head; + q->head = (q->head + 1) % q->ndesc; + + desc = &q->desc[idx]; + entry = &q->entry[idx]; + + if (buf[0].skip_unmap) + entry->skip_buf0 = true; + entry->skip_buf1 = i == nbufs - 1; + + entry->dma_addr[0] = buf[0].addr; + entry->dma_len[0] = buf[0].len; + + ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len); + if (i < nbufs - 1) { + entry->dma_addr[1] = buf[1].addr; + entry->dma_len[1] = buf[1].len; + buf1 = buf[1].addr; + ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len); + if (buf[1].skip_unmap) + entry->skip_buf1 = true; + } + + if (i == nbufs - 1) + ctrl |= MT_DMA_CTL_LAST_SEC0; + else if (i == nbufs - 2) + ctrl |= MT_DMA_CTL_LAST_SEC1; + + WRITE_ONCE(desc->buf0, cpu_to_le32(buf0)); + WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); + WRITE_ONCE(desc->info, cpu_to_le32(info)); + WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); + + q->queued++; + } + + q->entry[idx].txwi = txwi; + q->entry[idx].skb = skb; + q->entry[idx].wcid = 0xffff; + + return idx; +} + +#if 0 +static int +mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q, + struct mt76_queue_buf *buf, int nbufs, u32 info, struct sk_buff *skb, void *txwi, void *rxwi) { struct mt76_queue_entry *entry; @@ -286,7 +387,7 @@ return idx; } - +#endif static void mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx, struct mt76_queue_entry *prev_e) @@ -315,7 +416,32 @@ mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q) { wmb(); - Q_WRITE(dev, q, cpu_idx, q->head); +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + { + if(dev->slot_id == 0) + { + if(q->hw_idx == TX_QUEUE0_INDEX || q->hw_idx == TX_QUEUE1_INDEX) + pAd.writel_api(q->head, &q->regs->cpu_idx, q); + else if(q->hw_idx == 1 && ((q->flags) & MT_QFLAG_WED)) + writel(q->head, (void *)(wed_base_addr + WED_RX1_CTRL0 + 8)); + else + writel(q->head, &q->regs->cpu_idx); + } + else + { + if(q->hw_idx == TX_QUEUE0_INDEX || q->hw_idx == TX_QUEUE1_INDEX) + pAd_1.writel_api(q->head, &q->regs->cpu_idx, q); + else if(q->hw_idx == 1 && ((q->flags) & MT_QFLAG_WED)) + writel(q->head, (void *)(wed_base_addr_1 + WED_RX1_CTRL0 + 8)); + else + writel(q->head, &q->regs->cpu_idx); + } + } + else +#endif + writel(q->head, &q->regs->cpu_idx); + //Q_WRITE(dev, q, cpu_idx, q->head); } static void @@ -331,7 +457,17 @@ if (flush) last = -1; else - last = Q_READ(dev, q, dma_idx); + { +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + last = woe_read_1(dev, q); + else + last = readl(&q->regs->dma_idx); +#else + last = readl(&q->regs->dma_idx); +#endif + } + while (q->queued > 0 && q->tail != last) { mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry); @@ -343,7 +479,17 @@ } if (!flush && q->tail == last) - last = Q_READ(dev, q, dma_idx); + { +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + last = woe_read_1(dev, q); + else + last = readl(&q->regs->dma_idx); +#else + last = readl(&q->regs->dma_idx); +#endif + } + } spin_unlock_bh(&q->cleanup_lock); @@ -482,7 +628,7 @@ buf.len = skb->len; spin_lock_bh(&q->lock); - mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL, NULL); + mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL); mt76_dma_kick_queue(dev, q); spin_unlock_bh(&q->lock); @@ -559,7 +705,8 @@ goto unmap; return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf, - tx_info.info, tx_info.skb, t, NULL); + tx_info.info, tx_info.skb, t); + unmap: for (n--; n > 0; n--) @@ -585,7 +732,48 @@ return ret; } +int +mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q) +{ + dma_addr_t addr; + void *buf; + int frames = 0; + int len = SKB_WITH_OVERHEAD(q->buf_size); + int offset = q->buf_offset; + + if (!q->ndesc) + return 0; + + spin_lock_bh(&q->lock); + + while (q->queued < q->ndesc - 1) { + struct mt76_queue_buf qbuf; + + buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC); + if (!buf) + break; + + addr = dma_map_single(dev->dev, buf, len, DMA_FROM_DEVICE); + if (unlikely(dma_mapping_error(dev->dev, addr))) { + skb_free_frag(buf); + break; + } + + qbuf.addr = addr + offset; + qbuf.len = len - offset; + mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL); + frames++; + } + + if (frames) + mt76_dma_kick_queue(dev, q); + + spin_unlock_bh(&q->lock); + + return frames; +} +#if 0 static int mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q) { @@ -650,7 +838,8 @@ return frames; } - +#endif +#if 0 int mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset) { @@ -704,6 +893,44 @@ #endif } EXPORT_SYMBOL_GPL(mt76_dma_wed_setup); +#endif + +#ifdef CONFIG_SOC_WOE +static int +mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset) +{ + //struct mtk_wed_device *wed = &dev->mmio.wed; + int ret, type, ring, i; + u8 flags = q->flags; + type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags); + ring = FIELD_GET(MT_QFLAG_WED_RING, q->flags); + switch (type) { + case MT76_WED_Q_TXFREE: + /* WED txfree queue needs ring to be initialized before setup */ + q->flags = 0; + for (i = 0; i < q->ndesc; i++) + q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); + writel(0, &q->regs->cpu_idx); + writel(0, &q->regs->dma_idx); + writel(q->desc_dma, &q->regs->desc_base); + writel(q->ndesc, &q->regs->ring_size); + q->head = readl(&q->regs->dma_idx); + q->tail = q->head; + mt76_dma_rx_fill(dev, q); + q->flags = flags; +#ifdef CONFIG_SOC_WOE + q->wed_regs = WED_RX1_CTRL0; + ret = mtk_wed_device_txfree_ring_setup(dev, q->regs); +#endif + break; + default: + ret = 0; + } + + return ret; +} +#endif + static int mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q, @@ -715,7 +942,21 @@ spin_lock_init(&q->lock); spin_lock_init(&q->cleanup_lock); +#ifdef CONFIG_SOC_WOE + /*tx queue0 & tx queue1*/ + if(woe_enable()) + { + if(idx == TX_QUEUE0_INDEX || idx == TX_QUEUE1_INDEX) + q->regs = dev->mmio.regs + ring_base + (idx - TX_QUEUE0_INDEX) * MT_RING_SIZE; + else + q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; + } + else + q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; +#else q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; +#endif + q->ndesc = n_desc; q->buf_size = bufsize; q->hw_idx = idx; @@ -730,12 +971,27 @@ if (!q->entry) return -ENOMEM; - ret = mt76_dma_wed_setup(dev, q, false); - if (ret) - return ret; +#ifdef CONFIG_SOC_WOE + /*tx queue0 & queue1*/ + if(woe_enable()) + { + if(idx == TX_QUEUE0_INDEX || idx == TX_QUEUE1_INDEX) + mt76_dma_queue_reset_woe(dev, q); + else + { + if (q->flags != MT_WED_Q_TXFREE) + mt76_dma_queue_reset(dev, q); + } + ret = mt76_dma_wed_setup(dev, q, false); + if(ret) + return ret; + } + else + mt76_dma_queue_reset(dev, q); +#else - if (q->flags != MT_WED_Q_TXFREE) mt76_dma_queue_reset(dev, q); +#endif return 0; } @@ -783,14 +1039,25 @@ q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); mt76_dma_rx_cleanup(dev, q); - - mt76_dma_wed_setup(dev, q, true); - - if (q->flags != MT_WED_Q_TXFREE) { +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + { + mt76_dma_wed_setup(dev, q, true); + + if (q->flags != MT_WED_Q_TXFREE) { + mt76_dma_sync_idx(dev, q); + mt76_dma_rx_fill(dev, q); + } + } + else + { mt76_dma_sync_idx(dev, q); mt76_dma_rx_fill(dev, q); } - +#else + mt76_dma_sync_idx(dev, q); + mt76_dma_rx_fill(dev, q); +#endif if (!q->rx_head) return; @@ -798,6 +1065,7 @@ q->rx_head = NULL; } + static void mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data, int len, bool more, u32 info) @@ -828,22 +1096,41 @@ static int mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget) { - int len, data_len, done = 0, dma_idx; + int len, data_len, done = 0; struct sk_buff *skb; unsigned char *data; - bool check_ddone = false; + //bool check_ddone = false; bool more; - +#ifdef CONFIG_SOC_WOE + int dma_idx; + bool check_ddone = false; +#endif +#if 0 if (IS_ENABLED(CONFIG_NET_MEDIATEK_SOC_WED) && q->flags == MT_WED_Q_TXFREE) { dma_idx = Q_READ(dev, q, dma_idx); check_ddone = true; } +#endif + /*if whnat enable && rxq_mcu_wa*/ +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + { + if(q->flags == MT_WED_Q_TXFREE) + { + if(dev->slot_id == 0) + dma_idx = readl((void *)(wed_base_addr + WED_RX1_CTRL0 + 12)); + else + dma_idx = readl((void *)(wed_base_addr_1 + WED_RX1_CTRL0 + 12)); + check_ddone = 1; + } + } +#endif while (done < budget) { bool drop = false; u32 info; - +#if 0 if (check_ddone) { if (q->tail == dma_idx) dma_idx = Q_READ(dev, q, dma_idx); @@ -851,6 +1138,21 @@ if (q->tail == dma_idx) break; } +#endif +#ifdef CONFIG_SOC_WOE + if(check_ddone && woe_enable()) + { + if(q->tail == dma_idx) + { + if(dev->slot_id == 0) + dma_idx = readl((void *)(wed_base_addr + WED_RX1_CTRL0 + 12)); + else + dma_idx = readl((void *)(wed_base_addr_1 + WED_RX1_CTRL0 + 12)); + } + if(q->tail == dma_idx) + break; + } +#endif data = mt76_dma_dequeue(dev, q, false, &len, &info, &more, &drop); @@ -906,23 +1208,118 @@ mt76_dma_rx_fill(dev, q); return done; } +int dev_dbdc = 0; +EXPORT_SYMBOL(dev_dbdc); int mt76_dma_rx_poll(struct napi_struct *napi, int budget) { struct mt76_dev *dev; int qid, done = 0, cur; +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + void * pkt=NULL; + int bReschedule=0; + struct sk_buff *skb; + int npu_done=0; + unsigned char band = 0; +#endif dev = container_of(napi->dev, struct mt76_dev, napi_dev); qid = napi - dev->napi; rcu_read_lock(); +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + if(npu_enable()) + { + if(dev_dbdc) + { + if(qid != MT_RXQ_MAIN && qid != MT_RXQ_BAND1) + { + do { + cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done); + mt76_rx_poll_complete(dev, qid, napi); + done += cur; + } while (cur && done < budget); + } + else + { + if(qid == MT_RXQ_MAIN) + band = 0; + else if(qid == MT_RXQ_BAND1) + band = 1; + while (npu_done < budget) + { + if(fromHostadptPktHandle_hook) + pkt = fromHostadptPktHandle_hook(band, &bReschedule); + if(pkt) + { npu_done++; + skb=(struct sk_buff *)pkt; + dev->drv->rx_skb(dev, &dev->q_rx[qid] - dev->q_rx, skb, 0); + } + else + break; + + mt76_rx_poll_complete(dev, qid, napi); + } + rcu_read_unlock(); + if(npu_done < budget && napi_complete(napi)) + dev->drv->rx_poll_complete(dev, qid); + return npu_done; + } + } + else + { + do { + cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done); + mt76_rx_poll_complete(dev, qid, napi); + done += cur; + } while (cur && done < budget && qid!=0); + do { + + unsigned char band = dev->slot_id; + + if(fromHostadptPktHandle_hook){ + pkt = fromHostadptPktHandle_hook(band, &bReschedule); + } + + if(pkt) + { npu_done++; + skb=(struct sk_buff *)pkt; + dev->drv->rx_skb(dev, 0, skb, 0); + continue; + + }else + { + mt76_rx_poll_complete(dev, 0, napi); + rcu_read_unlock(); + if(napi_complete(napi)) + dev->drv->rx_poll_complete(dev, qid); + return 0; + } + mt76_rx_poll_complete(dev, 0, napi); + rcu_read_unlock(); + if(napi_complete(napi)) + dev->drv->rx_poll_complete(dev, qid); + return 0; + + } while (npu_done < budget && qid==0); + } + } + else + { + do { + cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done); + mt76_rx_poll_complete(dev, qid, napi); + done += cur; + } while (cur && done < budget); + } +#else do { cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done); mt76_rx_poll_complete(dev, qid, napi); done += cur; } while (cur && done < budget); - +#endif rcu_read_unlock(); if (done < budget && napi_complete(napi)) @@ -931,7 +1328,6 @@ return done; } EXPORT_SYMBOL_GPL(mt76_dma_rx_poll); - static int mt76_dma_init(struct mt76_dev *dev, int (*poll)(struct napi_struct *napi, int budget)) @@ -1003,10 +1399,10 @@ mt76_free_pending_txwi(dev); mt76_free_pending_rxwi(dev); - +#if 0 if (mtk_wed_device_active(&dev->mmio.wed)) mtk_wed_device_detach(&dev->mmio.wed); - +#endif mt76_free_pending_rxwi(dev); } EXPORT_SYMBOL_GPL(mt76_dma_cleanup); diff -uNr old/dma.h new/dma.h --- old/dma.h 2023-05-08 12:34:37.151919000 +0800 +++ new/dma.h 2023-05-05 19:28:31.675108000 +0800 @@ -57,6 +57,6 @@ int mt76_dma_rx_poll(struct napi_struct *napi, int budget); void mt76_dma_attach(struct mt76_dev *dev); void mt76_dma_cleanup(struct mt76_dev *dev); -int mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset); +//int mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset); #endif diff -uNr old/mac80211.c new/mac80211.c --- old/mac80211.c 2023-05-08 12:34:37.440923000 +0800 +++ new/mac80211.c 2023-05-06 12:42:36.261798000 +0800 @@ -1342,9 +1342,11 @@ while ((skb = __skb_dequeue(&dev->rx_skb[q])) != NULL) { mt76_check_sta(dev, skb); +#if 0 if (mtk_wed_device_active(&dev->mmio.wed)) __skb_queue_tail(&frames, skb); else +#endif mt76_rx_aggr_reorder(skb, &frames); } diff -uNr old/Makefile new/Makefile --- old/Makefile 2023-05-08 12:34:37.443916000 +0800 +++ new/Makefile 2023-05-05 19:32:00.954057000 +0800 @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only -EXTRA_CFLAGS += -Werror -DCONFIG_MT76_LEDS +EXTRA_CFLAGS += -DCONFIG_MT76_LEDS obj-m := mt76.o obj-$(CONFIG_MT76_USB) += mt76-usb.o obj-$(CONFIG_MT76_SDIO) += mt76-sdio.o @@ -9,7 +9,7 @@ mt76-y := \ mmio.o util.o trace.o dma.o mac80211.o debugfs.o eeprom.o \ - tx.o agg-rx.o mcu.o + tx.o agg-rx.o mcu.o mt76_npu_offload.o mt76-$(CONFIG_BB_SOC) += bb_soc.o mt76-$(CONFIG_PCI) += pci.o mt76-$(CONFIG_NL80211_TESTMODE) += testmode.o diff -uNr old/mmio.c new/mmio.c --- old/mmio.c 2022-12-10 20:11:05.000000000 +0800 +++ new/mmio.c 2023-05-08 11:07:00.842290000 +0800 @@ -5,6 +5,9 @@ #include "mt76.h" #include "trace.h" +#ifdef CONFIG_SOC_WOE +#include "mt76_woe.h" +#endif static u32 mt76_mmio_rr(struct mt76_dev *dev, u32 offset) { @@ -74,11 +77,19 @@ dev->mmio.irqmask &= ~clear; dev->mmio.irqmask |= set; if (addr) { +#if 0 if (mtk_wed_device_active(&dev->mmio.wed)) mtk_wed_device_irq_set_mask(&dev->mmio.wed, dev->mmio.irqmask); else mt76_mmio_wr(dev, addr, dev->mmio.irqmask); +#endif +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + mtk_wed_irq_set_mask_woe(dev, dev->mmio.irqmask); + else +#endif + mt76_mmio_wr(dev, addr, dev->mmio.irqmask); } spin_unlock_irqrestore(&dev->mmio.irq_lock, flags); } diff -uNr old/mt76_connac_mac.c new/mt76_connac_mac.c --- old/mt76_connac_mac.c 2022-12-10 20:11:05.000000000 +0800 +++ new/mt76_connac_mac.c 2023-05-05 19:29:27.524087000 +0800 @@ -4,6 +4,7 @@ #include "mt76_connac.h" #include "mt76_connac2_mac.h" #include "dma.h" +#include "mt76_woe.h" #define HE_BITS(f) cpu_to_le16(IEEE80211_RADIOTAP_HE_##f) #define HE_PREP(f, m, v) le16_encode_bits(le32_get_bits(v, MT_CRXV_HE_##m),\ @@ -255,6 +256,13 @@ int ring_base, u32 flags) { int i, err; +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + { + if(idx == TX_QUEUE0_INDEX || idx == TX_QUEUE1_INDEX) + ring_base = 0xd7300; + } +#endif err = mt76_init_tx_queue(phy, 0, idx, n_desc, ring_base, flags); if (err < 0) diff -uNr old/mt76_connac_mcu.c new/mt76_connac_mcu.c --- old/mt76_connac_mcu.c 2023-05-08 12:34:37.352925000 +0800 +++ new/mt76_connac_mcu.c 2023-05-06 13:32:44.309587000 +0800 @@ -1223,17 +1223,18 @@ ba->tid = params->tid; } EXPORT_SYMBOL_GPL(mt76_connac_mcu_sta_ba_tlv); - +#if 0 int mt76_connac_mcu_sta_wed_update(struct mt76_dev *dev, struct sk_buff *skb) { +#if 0 if (!mtk_wed_device_active(&dev->mmio.wed)) return 0; - +#endif return mtk_wed_device_update_msg(&dev->mmio.wed, WED_WO_STA_REC, skb->data, skb->len); } EXPORT_SYMBOL_GPL(mt76_connac_mcu_sta_wed_update); - +#endif int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif *mvif, struct ieee80211_ampdu_params *params, int cmd, bool enable, bool tx) @@ -1259,10 +1260,11 @@ mt76_connac_mcu_wtbl_ba_tlv(dev, skb, params, enable, tx, sta_wtbl, wtbl_hdr); +#if 0 ret = mt76_connac_mcu_sta_wed_update(dev, skb); if (ret) return ret; - +#endif ret = mt76_mcu_skb_send_msg(dev, skb, cmd, true); if (ret) return ret; @@ -1273,10 +1275,11 @@ mt76_connac_mcu_sta_ba_tlv(skb, params, enable, tx); +#if 0 ret = mt76_connac_mcu_sta_wed_update(dev, skb); if (ret) return ret; - +#endif return mt76_mcu_skb_send_msg(dev, skb, cmd, true); } EXPORT_SYMBOL_GPL(mt76_connac_mcu_sta_ba); @@ -2715,10 +2718,11 @@ if (ret) return ret; +#if 0 ret = mt76_connac_mcu_sta_wed_update(dev, skb); if (ret) return ret; - +#endif return mt76_mcu_skb_send_msg(dev, skb, mcu_cmd, true); } EXPORT_SYMBOL_GPL(mt76_connac_mcu_add_key); diff -uNr old/mt76_connac_mcu.h new/mt76_connac_mcu.h --- old/mt76_connac_mcu.h 2023-05-08 12:34:37.166914000 +0800 +++ new/mt76_connac_mcu.h 2023-05-06 13:32:15.467595000 +0800 @@ -1913,7 +1913,7 @@ int mt76_connac_mcu_restart(struct mt76_dev *dev); int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index, u8 rx_sel, u8 val); -int mt76_connac_mcu_sta_wed_update(struct mt76_dev *dev, struct sk_buff *skb); +//int mt76_connac_mcu_sta_wed_update(struct mt76_dev *dev, struct sk_buff *skb); int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm, const char *fw_wa); int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name); diff -uNr old/mt76.h new/mt76.h --- old/mt76.h 2023-05-08 12:34:37.461925000 +0800 +++ new/mt76.h 2023-05-06 12:44:21.192803000 +0800 @@ -13,7 +13,7 @@ #include #include #include -#include +//#include #include #include #include "util.h" @@ -604,8 +604,9 @@ void __iomem *regs; spinlock_t irq_lock; u32 irqmask; - +#if 0 struct mtk_wed_device wed; +#endif }; struct mt76_rx_status { @@ -913,6 +914,9 @@ struct mt76_connac2_fw_trailer *wm_hdr; struct mt76_connac2_fw_trailer *wa_hdr; const char *bin_file_name; +#if defined(CONFIG_SOC_WOE) || defined(TCSUPPORT_NPU_WIFI_OFFLOAD) + u32 slot_id; +#endif }; struct mt76_power_limits { diff -uNr old/mt76_npu_offload.c new/mt76_npu_offload.c --- old/mt76_npu_offload.c 1970-01-01 08:00:00.000000000 +0800 +++ new/mt76_npu_offload.c 2023-05-08 16:29:43.963963000 +0800 @@ -0,0 +1,372 @@ +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD +#include "mt76_npu_offload.h" +extern unsigned long int *dramReorderNodeBase; +/* +extern int setonce; + +extern unsigned long int *HCounter_Base; +extern unsigned long int *NCounter_Base; +extern unsigned long int *NCounter2G_Base; +extern unsigned long int *NCounterU_Base; + +*/ + +unsigned long int *HCounter_Base;//, *dbg_flag, *dbg2_flag; +unsigned long int *NCounter_Base; + +unsigned long int *NCounter2G_Base, *NCounterU_Base;//, *dbg_flag, *dbg2_flag; +unsigned long int *dramReorderNodeBase; +int setonce=0; + + +int npu_enable_chk = 1; +extern int dev_dbdc; +void npu_init_rxD(struct mt7915_dev *dev,struct pci_dev *pdev) +{ + int isMailBoxSuccess=0; + int ring_size=1536; + unsigned char band_idx = 0; + if (pdev->bus) + band_idx = (pdev->bus->self->devfn >> 3) & 0x1f; + if(dev_dbdc) + band_idx = 0; + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_DESC(band_idx, ring_size); + if(isMailBoxSuccess != 1) + printk("Error: NPU_WIFI_OFFLOAD Set RXD ring size fail\n"); + if(dev_dbdc) + { + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_DESC(1, ring_size); + if(isMailBoxSuccess != 1) + printk("Error: NPU_WIFI_OFFLOAD Set RXD ring size fail\n"); + } +} +EXPORT_SYMBOL_GPL(npu_init_rxD); +void wifi_offload_init_npu(struct pci_dev *pdev,struct mt7915_dev *dev,int flag) +{ + + int isMailBoxSuccess = 0; + unsigned char band_idx = 0,ring_idx = 0, pcidevindex = 0; + npu_info_t get_RingBase; + dbg_counter_t get_CounterBase; + unsigned short int node_index = 0, pop_index = 0, max_num; + struct sk_buff *skb_pkt = NULL; + unsigned long int pcie_pa, hcounter_pa; + unsigned int PciePortType; + struct hif_pci_rx_ring *rx_ring; + unsigned long int reorder_node_pa; + struct mt76_dev *mdev; + mdev = &dev->mt76; + struct mt7915_phy *phy; + phy=&dev->phy; + int countlen[3] ={47,44,15}; + int npuOffloadEn=1; + u32 hif1_ofs = 0; + int num,index; + pcie_pa=NULL; + if(npuOffloadEn){ + printk("npuOffload on mt76 init \n"); + if (pdev->bus){ + band_idx = (pdev->bus->self->devfn >> 3) & 0x1f; + printk("the value of pdev->bus->self->devfn is %d ,and the band_index is %d\n",pdev->bus->self->devfn,band_idx); + mdev->slot_id = (pdev->bus->self->devfn >> 3) & 0x1f; + } + if(dev_dbdc) + { + if(is_mt7916(mdev)) + { + band_idx = 0; + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_DRIVER_MODEL(band_idx, MT7916_D); + if(isMailBoxSuccess != 1) + printk("Error: 7915D 111 NPU_WIFI_OFFLOAD Set Dirver Model Fail\n"); + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_PCIE_PORT_TYPE(band_idx, P0__P0); + if(isMailBoxSuccess != 1) + printk("Error: 7915A NPU_WIFI_OFFLOAD Set PCIE PORT Fail\n"); + } + else + { + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_DRIVER_MODEL(band_idx, MT7915_D); + if(isMailBoxSuccess != 1) + printk("Error: 7915D 111 NPU_WIFI_OFFLOAD Set Dirver Model Fail\n"); + if(band_idx==0)//7915d use pcie0 + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_PCIE_PORT_TYPE(band_idx, P0_); + else//7915d use pcie1 + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_PCIE_PORT_TYPE(band_idx, P1_);//xflu 0404 + if(isMailBoxSuccess != 1) + printk("Error: 7915A NPU_WIFI_OFFLOAD Set PCIE PORT Fail\n"); + } + } + //DBG7915("Error: 7915D NPU_WIFI_OFFLOAD Set Dirver Model Fail\n"); + else + { + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_DRIVER_MODEL(band_idx, MT7915_A); + if(isMailBoxSuccess != 1) + printk("Error: 7915A NPU_WIFI_OFFLOAD Set Dirver Model Fail\n"); + else + printk("Error: 7915A NPU_WIFI_OFFLOAD Set Dirver Model success \n"); + + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_PCIE_PORT_TYPE(band_idx, P0__P0); + if(isMailBoxSuccess != 1) + printk("Error: 7915A NPU_WIFI_OFFLOAD Set PCIE PORT Fail\n"); + else + printk("Error: 7915A NPU_WIFI_OFFLOAD Set PCIE PORT success \n"); + + + } + + /****************set global setting(only once)**************/ + if((setonce != 1) && (setonce !=2)) + setonce = 1; + + if((setonce == 1)){ + printk("!!!! do phy and virtual address mapping\n"); + /**************debug count******************/ + + struct device *pdev_for_cnt; + + pdev_for_cnt=&pdev->dev; + HCounter_Base = dma_alloc_coherent(pdev_for_cnt, 0x200000, &hcounter_pa, GFP_KERNEL); + memset(HCounter_Base, 0x0, (HOST_COUNTER_SIZE*sizeof(unsigned long int))); + isMailBoxSuccess = WIFI_MAIL_API_GET_WAIT_DBG_COUNTER(3, &get_CounterBase); + NCounterU_Base = ioremap((phys_addr_t)get_CounterBase.errCount, (UTIL_COUNTER_NUM* sizeof(unsigned long int))); + if(isMailBoxSuccess != 1) + printk("Error: 7915D NPU_WIFI_OFFLOAD Get counter base fail\n"); + + for(index = 0; index < 2;index++) + { + isMailBoxSuccess = WIFI_MAIL_API_GET_WAIT_DBG_COUNTER(index, &get_CounterBase); + if(isMailBoxSuccess == 1) { + + if(index) + NCounter_Base = ioremap((phys_addr_t)get_CounterBase.errCount, (NPU_COUNTER_SIZE* sizeof(unsigned long int))); + else + NCounter2G_Base = ioremap((phys_addr_t)get_CounterBase.errCount, (NPU_COUNTER_SIZE* sizeof(unsigned long int))); + } + } + + if(NCounter2G_Base) + printk("the addr of NCounter2G_Base is %x \n",NCounter2G_Base); + /**************ba node******************/ + dramReorderNodeBase = dma_alloc_coherent(pdev_for_cnt, 0x200000, &reorder_node_pa, GFP_KERNEL); + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_DRAM_BA_NODE_ADDR(band_idx, reorder_node_pa); + if(isMailBoxSuccess != 1) + printk("Error: NPU_WIFI_OFFLOAD set BA Node in Dram base fail\n"); + setonce = 2; + } + pcie_pa = pci_resource_start(pdev, 0); //get pcie phy addr + if(dev_dbdc) + { + if(is_mt7916(mdev)) + { + printk("%s:%d mt7916d device !!!\n",__func__,__LINE__); + if (dev->hif2) + hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); + for(num = 0; num < 2; num++){ + if(num) + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_PCIE_ADDR(num, (pcie_pa + MT_RXQ_RING_BASE(MT_RXQ_MAIN) + 0x50 + hif1_ofs)); + else + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_PCIE_ADDR(num, (pcie_pa + MT_RXQ_RING_BASE(MT_RXQ_MAIN) + 0x40)); + } + } + else + { + printk("%s:%d mt7915d device !!!\n",__func__,__LINE__); + for(num = 0; num < 2; num++){ + if(num) + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_PCIE_ADDR(num, (pcie_pa + MT_RXQ_RING_BASE(MT_RXQ_MAIN) + 0x10)); + else + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_PCIE_ADDR(num, (pcie_pa + MT_RXQ_RING_BASE(MT_RXQ_MAIN))); + } + } + } +#if TCSUPPORT_NPU_WIFI_OFFLOAD || (defined(BB_SOC)&& defined(MULTI_INF_SUPPORT)) + else + { + printk("after :pci_resource_start= %x\n", pcie_pa); + isMailBoxSuccess = WIFI_MAIL_API_SET_WAIT_PCIE_ADDR(band_idx, (pcie_pa+0xd4500)); + if(isMailBoxSuccess != 1) + printk("%s:%d 7915A NPU_WIFI_OFFLOAD Set pcie base fail\n",__func__,__LINE__); + } +#endif + } +} +EXPORT_SYMBOL_GPL(wifi_offload_init_npu); +void get_npu_rxd(struct mt7915_dev *dev,struct pci_dev *pdev) +{ + npu_info_t get_RingBase_2g, get_RingBase_5g,get_RingBase; + int isMailBoxSuccess=0; + unsigned char band_idx = 0; + void __iomem *npu_regs; + if (pdev->bus) + band_idx = (pdev->bus->self->devfn >> 3) & 0x1f; + if(dev_dbdc) + band_idx = 0; + isMailBoxSuccess = WIFI_MAIL_API_GET_WAIT_RXDESC_BASE(band_idx, &get_RingBase_2g); + if(isMailBoxSuccess != 1) + printk("Error: NPU_WIFI_OFFLOAD get ring0 base fail\n"); + npu_regs=(NDIS_PHYSICAL_ADDRESS)get_RingBase_2g.info; + writel(npu_regs,&dev->mt76.q_rx[MT_RXQ_MAIN].regs->desc_base); + if(dev_dbdc) + { + isMailBoxSuccess = WIFI_MAIL_API_GET_WAIT_RXDESC_BASE(1, &get_RingBase_5g); + if(isMailBoxSuccess != 1) + printk("Error: NPU_WIFI_OFFLOAD get ring1 base fail\n"); + npu_regs=(NDIS_PHYSICAL_ADDRESS)get_RingBase_5g.info; + writel(npu_regs,&dev->mt76.q_rx[MT_RXQ_BAND1].regs->desc_base); + } +} +EXPORT_SYMBOL_GPL(get_npu_rxd); + + +int npu_enable(void) +{ + return npu_enable_chk; +} +void set_npu_enable(int enable) +{ + npu_enable_chk = enable; +} +EXPORT_SYMBOL_GPL(npu_enable); +EXPORT_SYMBOL_GPL(set_npu_enable); + + +int mt7915_npu_count(struct seq_file *s, void *data) +{ + //struct mt7915_dev *dev = dev_get_drvdata(s->private); + //struct mt76_dev *mdev = NULL; + seq_printf(s, "Version: 2.2.6.0\n"); + + + printk("show host pkt count:\n"); + printk("------Host Counter----------\n"); + printk("HOST_WHILE_COUNTER:\t\t%lu\n", HOST_COUNTER(HOST_WHILE_COUNT)); + printk("RESCHEDULE_COUNT:\t\t%lu\n", HOST_COUNTER(RESCHEDULE_COUNT)); + printk("PKT_NULL_COUNT:\t\t\t%lu\n",HOST_COUNTER(PKT_NULL_COUNT)); + printk("HOST_GET_2GPKT_COUNT:\t\t%lu\n", HOST_COUNTER(HOST_GET_2GPKT_COUNT)); + printk("HOST_GET_5GPKT_COUNT:\t\t%lu\n",HOST_COUNTER(HOST_GET_5GPKT_COUNT)); + + //printk("HOST_WHILE_COUNTER:\t\t%lu\nRESCHEDULE_COUNT:\t\t%lu\nNOT_DATA_2GPKT_COUNT:\t\t%lu\nNOT_DATA_5GPKT_COUNT:\t\t%lu\nHAS_CRESN_2GPKT_COUNT:\t\t%lu\nDEQ_PKT_COUNT:\t\t\t%lu\nPKT_NULL_COUNT:\t\t\t%lu\nHOST_GET_2GPKT_COUNT:\t\t%lu\nHOST_GET_5GPKT_COUNT:\t\t%lu\n", HOST_COUNTER(HOST_WHILE_COUNT), HOST_COUNTER(RESCHEDULE_COUNT), HOST_COUNTER(NOT_DATA_PKT_COUNT), HOST_COUNTER(HAS_CRESN_PKT_COUNT), HOST_COUNTER(DEQ_2GPKT_COUNT), HOST_COUNTER(DEQ_5GPKT_COUNT),HOST_COUNTER(PKT_NULL_COUNT), HOST_COUNTER(HOST_GET_2GPKT_COUNT), HOST_COUNTER(HOST_GET_5GPKT_COUNT)); + printk("========== NPU 5G Counter ===========\n"); + printk("get packet while count:\t\t%lu\n", NPU_COUNTER(NCounter_Base,WHILE_COUNT)); + printk("RX_DESC_DDONE\t\t\t%lu\n", NPU_COUNTER(NCounter_Base,RX_DESC_DDONE)); + printk("ALL_GET_PKT_COUNT\t\t%lu\n", NPU_COUNTER(NCounter_Base,ALL_GET_PKT_COUNT)); + //printk("ACCESS_PACKET\t\t\t%lu\n", NPU_COUNTER(NCounter_Base,ACCESS_PACKET)); + printk("DROP_PACKETS\t\t\t%lu\n", NPU_COUNTER(NCounter_Base,DROP_PACKETS)); + printk("TO_QDMA_COUNT\t\t\t%lu\n", NPU_COUNTER(NCounter_Base,TO_QDMA_COUNT)); + //printk("ALL_ENQ_PKT_COUNT\t\t%lu\n", NPU_COUNTER(NCounter_Base,ALL_ENQ_PKT_COUNT)); + //printk("ENQ_BUFID_FIAL_COUNT\t\t%lu\n", NPU_COUNTER(NCounter_Base,ENQ_BUFID_FIAL_COUNT)); + //printk("ENQ_BUFID_ERROR_COUNT:\t\t%lu\n",NPU_COUNTER(NCounter_Base, ENQ_BUFID_ERROR_COUNT)); + printk("GET_BUFID_FAIL\t\t\t%lu\n", NPU_COUNTER(NCounter_Base,GET_BUFID_FAIL)); + //printk("NO_BUFID\t\t\t%lu\n", NPU_COUNTER(NCounter_Base,NO_BUFID)); + printk("SCATTER_CNT_MORE1\t\t%lu\n", NPU_COUNTER(NCounter_Base, SCATTER_CNT_MORE1)); + printk("BIGGER_PACKET\t\t\t%lu\n", NPU_COUNTER(NCounter_Base,BIGGER_PACKET)); + + printk("------Enq & Deq Counter----------\n"); + printk("ENQ_DEQ_WHILE_COUNT\t\t%lu\n", NPU_COUNTER(NCounter_Base,ENQ_DEQ_WHILE_COUNT)); + printk("ENQ_SRAM_COUNT:\t\t\t%lu\n",NPU_COUNTER(NCounter_Base,ENQ_SRAM_COUNT)); + printk("ENQ_SRAM_FULL_COUNT:\t\t%lu\n",NPU_COUNTER(NCounter_Base,ENQ_SRAM_FULL_COUNT)); + printk("ENQ_SRAM_FAIL_COUNT:\t\t%lu\n",NPU_COUNTER(NCounter_Base,ENQ_SRAM_FAIL_COUNT)); + printk("DEQ_SRAM_COUNT:\t\t\t%lu\nDEQ_SRAM_FAIL_BUFID_COUNT:\t%lu\nDEQ_SRAM_FAIL_LEN_COUNT:\t%lu\n",NPU_COUNTER(NCounter_Base,DEQ_SRAM_COUNT),NPU_COUNTER(NCounter_Base, DEQ_SRAM_FAIL_BUFID_COUNT), NPU_COUNTER(NCounter_Base,DEQ_SRAM_FAIL_LEN_COUNT)); + //printk("DEQ_SRAM_NO_INFO_COUNT\t\t%lu\n", NPU_COUNTER(NCounter_Base, DEQ_SRAM_NO_INFO_COUNT)); + printk("TO_HOSTAPD_COUNT\t\t\t%lu\n", NPU_COUNTER(NCounter_Base, TO_HOSTAPD_COUNT)); + //printk("ENQ_DRAM_FAIL_COUNT:\t\t%lu\n",NPU_COUNTER(NCounter_Base, ENQ_DRAM_FAIL_COUNT)); + printk("HOST_APD_ERROR_COUNT:\t\t%lu\n", NPU_COUNTER(NCounter_Base, HOST_APD_ERROR_COUNT)); + + printk("------BA Counter----------\n"); + printk("BA1(in order):\t\t\t%lu\nBA2(Dupl Packet):\t\t%lu\nBA3(old packet):\t\t%lu\nBA4(with in window):\t\t%lu\nBA5(surpasses Win):\t\t%lu\nBA_AMSDU:\t\t\t%lu\n!AMPDU_COUNT:\t\t\t%lu\n",NPU_COUNTER(NCounter_Base, BA_IN_ORDER_PKT_COUNT),NPU_COUNTER(NCounter_Base, BA_DUPL_PKT_COUNT), NPU_COUNTER(NCounter_Base,BA_OLD_PKT_COUNT), NPU_COUNTER(NCounter_Base,BA_WITHIN_WS_PKT_COUNT), NPU_COUNTER(NCounter_Base, BA_POP_PKT_COUNT), NPU_COUNTER(NCounter_Base, BA_AMSDU_COUNT), NPU_COUNTER(NCounter_Base, AMPDU_COUNT)); + //printk("BA_NO_PKT_IN_LIST_COUNT:\t%lu\n", NPU_COUNTER(NCounter_Base, BA_NO_PKT_IN_LIST_COUNT)); + //printk("BA_NOT_DATA_PKT_COUNT:\t\t%lu\n", NPU_COUNTER(NCounter_Base, BA_NOT_DATA_PKT_COUNT)); + printk("BA_NO_MEM_COUNT:\t\t%lu\n", NPU_COUNTER(NCounter_Base, BA_NO_MEM_COUNT)); + //printk("BA_NODE_ALLOC_COUNT:\t\t%lu\n", NPU_COUNTER(NCounter_Base, BA_NODE_ALLOC_COUNT)); + //printk("BA_NODE_ALLOC_FAIL:\t\t%lu\n", NPU_COUNTER(NCounter_Base, BA_NODE_ALLOC_FAIL)); + printk("BA_AMSDU_MISS:\t\t\t%lu\n", NPU_COUNTER(NCounter_Base, BA_AMSDU_MISS)); + //printk("BA_TIMEOUT_FLUSH:\t\t%lu\n", NPU_COUNTER(NCounter_Base, BA_TIMEOUT_FLUSH)); + printk("BA_TIMEOUT_FLUSH100:\t\t%lu\n", NPU_COUNTER(NCounter_Base, BA_TIMEOUT_FLUSH100)); + printk("BA_TIMEOUT_FLUSH250:\t\t%lu\n", NPU_COUNTER(NCounter_Base, BA_TIMEOUT_FLUSH250)); + printk("BA_ENQ_DUP_SEQ:\t\t\t%lu\n", NPU_COUNTER(NCounter_Base, BA_ENQ_DUP_SEQ)); + printk("BA_REORDERING_NODE_ALLOC_COUNT\t%lu\n", NPU_COUNTER(NCounter_Base,BA_REORDERING_NODE_ALLOC_COUNT)); + printk("BA_REORDERING_NODE_ALLOC_DRAM_COUNT\t%lu\n", NPU_COUNTER(NCounter_Base,BA_REORDERING_NODE_ALLOC_DRAM_COUNT)); + printk("BA_REORDERING_NODE_FREE_COUNT\t%lu\n", NPU_COUNTER(NCounter_Base,BA_REORDERING_NODE_FREE_COUNT)); + printk("BA_REORDERINT_NODE_ALLOC_FAIL\t%lu\n", NPU_COUNTER(NCounter_Base,BA_REORDERINT_NODE_ALLOC_FAIL)); + + //printk("------QDMA return Counter----------\n"); + //printk("QDMA_RETURN_UNBIND_COUNT:\t%lu\n", NPU_COUNTER(NCounter_Base, QDMA_RETURN_UNBIND_COUNT)); + //printk("QDMA_RETURN_FAIL_COUNT:\t\t%lu\n", NPU_COUNTER(NCounter_Base, QDMA_RETURN_FAIL_COUNT)); + //printk("QDMA_RETURN_OK_COUNT:\t\t%lu\n", NPU_COUNTER(NCounter_Base, QDMA_RETURN_OK_COUNT)); + + printk("========== NPU 2.4G Counter ===========\n"); + printk("get packet while count:\t\t%lu\n", NPU_COUNTER(NCounter2G_Base,WHILE_COUNT)); + printk("RX_DESC_DDONE\t\t\t%lu\n", NPU_COUNTER(NCounter2G_Base,RX_DESC_DDONE)); + printk("ALL_GET_PKT_COUNT\t\t%lu\n", NPU_COUNTER(NCounter2G_Base,ALL_GET_PKT_COUNT)); + //printk("ACCESS_PACKET\t\t\t%lu\n", NPU_COUNTER(NCounter2G_Base,ACCESS_PACKET)); + printk("DROP_PACKETS\t\t\t%lu\n", NPU_COUNTER(NCounter2G_Base,DROP_PACKETS)); + printk("TO_QDMA_COUNT\t\t\t%lu\n", NPU_COUNTER(NCounter2G_Base,TO_QDMA_COUNT)); + //printk("ALL_ENQ_PKT_COUNT\t\t%lu\n", NPU_COUNTER(NCounter2G_Base,ALL_ENQ_PKT_COUNT)); + //printk("ENQ_BUFID_FIAL_COUNT\t\t%lu\n", NPU_COUNTER(NCounter2G_Base,ENQ_BUFID_FIAL_COUNT)); + //printk("ENQ_BUFID_ERROR_COUNT:\t\t%lu\n",NPU_COUNTER(NCounter2G_Base,ENQ_BUFID_ERROR_COUNT)); + printk("GET_BUFID_FAIL\t\t\t%lu\n", NPU_COUNTER(NCounter2G_Base,GET_BUFID_FAIL)); + //printk("NO_BUFID\t\t\t%lu\n", NPU_COUNTER(NCounter2G_Base,NO_BUFID)); + printk("SCATTER_CNT_MORE1\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, SCATTER_CNT_MORE1)); + printk("BIGGER_PACKET\t\t\t%lu\n", NPU_COUNTER(NCounter2G_Base,BIGGER_PACKET)); + + printk("------Enq & Deq Counter----------\n"); + printk("ENQ_DEQ_WHILE_COUNT\t\t%lu\n", NPU_COUNTER(NCounter2G_Base,ENQ_DEQ_WHILE_COUNT)); + printk("ENQ_SRAM_COUNT:\t\t\t%lu\n",NPU_COUNTER(NCounter2G_Base,ENQ_SRAM_COUNT)); + printk("ENQ_SRAM_FULL_COUNT:\t\t%lu\n",NPU_COUNTER(NCounter2G_Base,ENQ_SRAM_FULL_COUNT)); + printk("ENQ_SRAM_FAIL_COUNT:\t\t%lu\n",NPU_COUNTER(NCounter2G_Base,ENQ_SRAM_FAIL_COUNT)); + printk("DEQ_SRAM_COUNT:\t\t\t%lu\nDEQ_SRAM_FAIL_BUFID_COUNT:\t%lu\nDEQ_SRAM_FAIL_LEN_COUNT:\t%lu\n",NPU_COUNTER(NCounter2G_Base,DEQ_SRAM_COUNT),NPU_COUNTER(NCounter2G_Base, DEQ_SRAM_FAIL_BUFID_COUNT), NPU_COUNTER(NCounter2G_Base,DEQ_SRAM_FAIL_LEN_COUNT)); + //printk("DEQ_SRAM_NO_INFO_COUNT\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, DEQ_SRAM_NO_INFO_COUNT)); + printk("TO_HOSTAPD_COUNT:\t\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, TO_HOSTAPD_COUNT)); + //printk("ENQ_DRAM_FAIL_COUNT:\t\t%lu\n",NPU_COUNTER(NCounter2G_Base, ENQ_DRAM_FAIL_COUNT)); + printk("HOST_APD_ERROR_COUNT:\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, HOST_APD_ERROR_COUNT)); + + printk("------BA Counter----------\n"); + printk("BA1(in order):\t\t\t%lu\nBA2(Dupl Packet):\t\t%lu\nBA3(old packet):\t\t%lu\nBA4(with in window):\t\t%lu\nBA5(surpasses Win):\t\t%lu\nBA_AMSDU:\t\t\t%lu\n!AMPDU_COUNT:\t\t\t%lu\n",NPU_COUNTER(NCounter2G_Base, BA_IN_ORDER_PKT_COUNT),NPU_COUNTER(NCounter2G_Base, BA_DUPL_PKT_COUNT), NPU_COUNTER(NCounter2G_Base,BA_OLD_PKT_COUNT), NPU_COUNTER(NCounter2G_Base,BA_WITHIN_WS_PKT_COUNT), NPU_COUNTER(NCounter2G_Base, BA_POP_PKT_COUNT), NPU_COUNTER(NCounter2G_Base, BA_AMSDU_COUNT), NPU_COUNTER(NCounter2G_Base, AMPDU_COUNT)); + //printk("BA_NO_PKT_IN_LIST_COUNT:\t%lu\n", NPU_COUNTER(NCounter2G_Base, BA_NO_PKT_IN_LIST_COUNT)); + //printk("BA_NOT_DATA_PKT_COUNT:\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, BA_NOT_DATA_PKT_COUNT)); + printk("BA_NO_MEM_COUNT:\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, BA_NO_MEM_COUNT)); + //printk("BA_NODE_ALLOC_COUNT:\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, BA_NODE_ALLOC_COUNT)); + //printk("BA_NODE_ALLOC_FAIL:\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, BA_NODE_ALLOC_FAIL)); + printk("BA_AMSDU_MISS:\t\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, BA_AMSDU_MISS)); + //printk("BA_TIMEOUT_FLUSH:\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, BA_TIMEOUT_FLUSH)); + printk("BA_TIMEOUT_FLUSH100:\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, BA_TIMEOUT_FLUSH100)); + printk("BA_TIMEOUT_FLUSH250:\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, BA_TIMEOUT_FLUSH250)); + printk("BA_ENQ_DUP_SEQ:\t\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, BA_ENQ_DUP_SEQ)); + printk("BA_REORDERING_NODE_ALLOC_COUNT\t%lu\n", NPU_COUNTER(NCounter2G_Base,BA_REORDERING_NODE_ALLOC_COUNT)); + printk("BA_REORDERING_NODE_ALLOC_DRAM_COUNT\t%lu\n", NPU_COUNTER(NCounter2G_Base,BA_REORDERING_NODE_ALLOC_DRAM_COUNT)); + printk("BA_REORDERING_NODE_FREE_COUNT\t%lu\n", NPU_COUNTER(NCounter2G_Base,BA_REORDERING_NODE_FREE_COUNT)); + printk("BA_REORDERINT_NODE_ALLOC_FAIL\t%lu\n", NPU_COUNTER(NCounter2G_Base,BA_REORDERINT_NODE_ALLOC_FAIL)); + + //printk("------QDMA return Counter----------\n"); + //printk("QDMA_RETURN_UNBIND_COUNT:\t%lu\n", NPU_COUNTER(NCounter2G_Base, QDMA_RETURN_UNBIND_COUNT)); + //printk("QDMA_RETURN_FAIL_COUNT:\t\t%lu\n", NPU_COUNTER(NCounter2G_Base, QDMA_RETURN_FAIL_COUNT)); + //printk("QDMA_RETURN_OK_COUNT:\t\t%lu\n", NPU_COUNTER(NCounter_Base, QDMA_RETURN_OK_COUNT)); + + printk("=======================================\n"); + printk("============ QDMA Counter =============\n"); + + printk("QDMA_TXDESC_NULL_COUNT:\t\t%lu\n", NPU_COUNTER(NCounterU_Base,QDMA_TXDESC_NULL_COUNT)); + printk("QDMA_UNBIND_COUNT:\t\t%lu\n", NPU_COUNTER(NCounterU_Base,QDMA_UNBIND_COUNT)); + //printk("QDMA_TO_PPE_COUNT:\t\t%lu\n", NPU_COUNTER(NCounterU_Base,QDMA_TO_PPE_COUNT)); + printk("QDMA_DONE_COUNT:\t\t%lu\n", NPU_COUNTER(NCounterU_Base,QDMA_DONE_COUNT)); + printk("QDMA_FREE_BUFID_COUNT:\t\t%lu\n", NPU_COUNTER(NCounterU_Base,QDMA_FREE_BUFID_COUNT)); + printk("QDMA_TO_ENQ_FAIL_COUNT:\t\t%lu\n", NPU_COUNTER(NCounterU_Base,QDMA_TO_ENQ_FAIL_COUNT)); + //printk("QDMA_TO_ENQ_FAIL_COUNT2:\t%lu\n", NPU_COUNTER(NCounterU_Base,QDMA_TO_ENQ_FAIL_COUNT2)); + printk("QDMA_TX_DSCP_IDX_INVALID:\t\t%lu\n", NPU_COUNTER(NCounterU_Base,QDMA_TX_DSCP_IDX_INVALID)); + printk("QDMA_TX_DSCP_INFO_ERROR:\t\t%lu\n", NPU_COUNTER(NCounterU_Base,QDMA_TX_DSCP_INFO_ERROR)); + printk("QDMA_DONE_DROP_BIT_ERROR:\t\t%lu\n", NPU_COUNTER(NCounterU_Base,QDMA_DONE_DROP_BIT_ERROR)); + //printk("QDMA_TXDESC_PUSH_COUNT:\t\t%lu\n", NPU_COUNTER(NCounterU_Base,QDMA_TXDESC_PUSH_COUNT)); + //printk("QDMA_TXDESC_PUSH2_COUNT:\t\t%lu\n", NPU_COUNTER(NCounterU_Base,QDMA_TXDESC_PUSH2_COUNT)); + //printk("QDMA_TXDESC_POP_COUNT:\t\t%lu\n", NPU_COUNTER(NCounterU_Base,QDMA_TXDESC_POP_COUNT)); + + printk("============ Bufid Counter ==========\n"); + printk("SKB_ALLOC_BUFID_COUNT\t\t%lu\n", NPU_COUNTER(NCounterU_Base,SKB_ALLOC_BUFID_COUNT)); + printk("SKB_FREE_BUFID_COUNT\t\t%lu\n", NPU_COUNTER(NCounterU_Base,SKB_FREE_BUFID_COUNT)); + printk("SKB_BUFID_ALLOC_FAIL\t\t%lu\n", NPU_COUNTER(NCounterU_Base,SKB_BUFID_ALLOC_FAIL)); + + return 0; +} +EXPORT_SYMBOL_GPL(mt7915_npu_count); + + + +#endif diff -uNr old/mt76_npu_offload.h new/mt76_npu_offload.h --- old/mt76_npu_offload.h 1970-01-01 08:00:00.000000000 +0800 +++ new/mt76_npu_offload.h 2023-05-05 15:19:57.964110000 +0800 @@ -0,0 +1,149 @@ +#ifndef NPU_OFFLOAD_H +#define NPU_OFFLOAD_H +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + +#include "modules/npu/wifi_mail.h" +#include "mt7915/mt7915.h" +#include "dma.h" +#include "mt7915/mac.h" +#include "mt76.h" + +#include +#include +#include + +#ifdef CONFIG_SOC_WOE +#include "mt76_woe.h" +#endif + + +#define BAND5G_IDX 1 +#define BAND2G_IDX 0 + + +#define HOST_COUNTER_SIZE 5 +#define NPU_MAX_TYPE 3 + + + + + +#define HOST_COUNTER(i) (*((unsigned long int *)((unsigned long int)HCounter_Base + (i << 2)))) +#define NPU_COUNTER(addr,i) (*((unsigned long int *)((unsigned long int)addr + (i << 2)))) +#define HOST_COUNTER_ADDR(i) ((unsigned long int)HCounter_Base + (i << 2)) +#define NPU_COUNTER_ADDR(addr,i) ((unsigned long int)addr + (i << 2)) + +enum NPU_OFFLOAD_COUNTER_OFFSET +{ + HOST_WHILE_COUNT = 0, //00 + RESCHEDULE_COUNT = 1, //01 + PKT_NULL_COUNT, //02 + HOST_GET_2GPKT_COUNT, //03 + HOST_GET_5GPKT_COUNT, //04 + HCOUNTER_BOTTOM // +}; + +typedef enum { + P0_ = 0, + P1_, + P0__P0, + P0__P1 +} PortType_t; + +enum COUNTER_OFFSET{ + GET_BUFID_FAIL = 0, //00v + WHILE_COUNT = 1, //01v + ALL_GET_PKT_COUNT, //03v + DROP_PACKETS, //04v + //ENQ_BUFID_FIAL_COUNT, //05v + //ALL_ENQ_PKT_COUNT, //06v + ENQ_DEQ_WHILE_COUNT, //07v + ENQ_SRAM_COUNT, //08v + ENQ_SRAM_FULL_COUNT, //09vv + ENQ_SRAM_FAIL_COUNT, //09v + DEQ_SRAM_COUNT, //11v + DEQ_SRAM_FAIL_BUFID_COUNT, //12v + DEQ_SRAM_FAIL_LEN_COUNT, //13v + //DEQ_SRAM_NO_INFO_COUNT, //14v + TO_HOSTAPD_COUNT, //15vv + //ENQ_DRAM_FAIL_COUNT, //16v + //ENQ_BUFID_ERROR_COUNT, //17v + BA_IN_ORDER_PKT_COUNT, //18v + BA_DUPL_PKT_COUNT, //19v + BA_OLD_PKT_COUNT, //20v + BA_WITHIN_WS_PKT_COUNT, //21v + BA_POP_PKT_COUNT, //22v + //BA_NO_PKT_IN_LIST_COUNT, //23v + BA_AMSDU_COUNT, //24v + AMPDU_COUNT, //25v + //BA_NOT_DATA_PKT_COUNT, //26v + //BA_RETURN_ERROR_COUNT, //27v + BA_NO_MEM_COUNT, //28v + TO_QDMA_COUNT, //29v + TO_QDMA_COUNT_88, + TO_QDMA_COUNT_512, + TO_QDMA_COUNT_1518, + //ACCESS_PACKET, //30v + HOST_APD_ERROR_COUNT, //31v + //QDMA_RETURN_UNBIND_COUNT, //32v + QDMA_RETURN_FAIL_COUNT, //33v + //QDMA_RETURN_OK_COUNT, //34v + SCATTER_CNT_MORE1, //35v + BIGGER_PACKET, //36v + //BA_NODE_ALLOC_FAIL, //37 + //BA_NODE_ALLOC_COUNT, //38 + BA_AMSDU_MISS, //39 + //BA_TIMEOUT_FLUSH, //40 + RX_DESC_DDONE, //41 + BA_TIMEOUT_FLUSH100, //42 + BA_TIMEOUT_FLUSH250, //43 + BA_ENQ_DUP_SEQ, //vv + BA_REORDERING_NODE_FREE_COUNT, //10vv + BA_REORDERINT_NODE_ALLOC_FAIL, //11vv + BA_REORDERING_NODE_ALLOC_COUNT, //12vv + BA_REORDERING_NODE_ALLOC_DRAM_COUNT,//vv + COUNTER_BOTTOM //47 +}; +#define NPU_COUNTER_SIZE COUNTER_BOTTOM +#define UTIL_COUNTER_NUM UCOUNTER_BOTTOM + +enum COUNTER_OFFSET_UTIL{ + QDMA_TXDESC_NULL_COUNT=0, //0vv + QDMA_FREE_BUFID_COUNT, //1vv + QDMA_UNBIND_COUNT, //2vv + QDMA_TO_ENQ_FAIL_COUNT, //3vv + QDMA_TO_ENQ_FAIL_COUNT2, //4 + //QDMA_TO_PPE_COUNT, //5 + QDMA_DONE_COUNT, //6vv + SKB_FREE_BUFID_COUNT, //7vv + SKB_ALLOC_BUFID_COUNT, //8vv + SKB_BUFID_ALLOC_FAIL, //9vv + QDMA_TX_DSCP_IDX_INVALID, //13vv + QDMA_TX_DSCP_INFO_ERROR, //14vv + QDMA_DONE_DROP_BIT_ERROR, //15 + //QDMA_TXDESC_PUSH_COUNT, //16 + //QDMA_TXDESC_PUSH2_COUNT, //17 + //QDMA_TXDESC_POP_COUNT, //18 + UCOUNTER_BOTTOM //19 +}; + + +#define ra_dma_addr_t unsigned long long +typedef ra_dma_addr_t NDIS_PHYSICAL_ADDRESS; +typedef void *PNDIS_PACKET; + +void wifi_offload_init_npu(struct pci_dev *pdev,struct mt7915_dev *dev,int flag); +void npu_init_rxD(struct mt7915_dev *dev,struct pci_dev *pdev); + + +void get_npu_rxd(struct mt7915_dev *dev,struct pci_dev *pdev); +int npu_enable(void); +void set_npu_enable(int enable); + +int mt7915_npu_count(struct seq_file *s, void *data); + + + + +#endif +#endif diff -uNr old/mt76_woe.h new/mt76_woe.h --- old/mt76_woe.h 1970-01-01 08:00:00.000000000 +0800 +++ new/mt76_woe.h 2023-05-06 17:30:11.296627000 +0800 @@ -0,0 +1,542 @@ +#ifndef __MT76_WOE_E_H +#define __MT76_WOE_E_H +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "util.h" +#include "testmode.h" +#include "mt7915/mt7915.h" +#include "mt7915/mac.h" +#include "dma.h" +#include "mt76.h" +typedef unsigned char UINT8; +typedef unsigned short UINT16; +typedef unsigned int UINT32; +typedef int INT32; +typedef unsigned char BOOLEAN; +typedef unsigned long ULONG; +typedef unsigned char UCHAR; +typedef void VOID; +typedef VOID *PVOID; +typedef int INT; +typedef UCHAR * PUCHAR; +#define NDIS_STATUS_SUCCESS 0x00 +#define NDIS_STATUS_FAILURE 0x01 +#define CHIP_ID_WOE 0x7915 +#define WHNAT_0 0 +#define WHNAT_1 1 +typedef unsigned short USHORT; +typedef signed char CHAR; +typedef unsigned char *PUINT8; +#define TRUE 1 +#define WED_RX1_CTRL0 0x00000410 +#define WED_RX0_CTRL0 0x00000400 +//#define MT_INT_WED_MASK_CSR 0xd7204 +struct mt76_queue_woe { + struct mt76_queue_regs __iomem *regs; + int ndesc; +}; +struct woe_need{ + unsigned int ChipID; + unsigned int tx_res_num; + BOOLEAN whnat_en; + //struct hif_pci_tx_ring_desc tx_ring_layout[2]; + struct mt76_queue_woe mt76_queue_info; + UINT32 int_enable_mask; + UINT32 token_tx_cnt; + UINT32 hw_tx_token_cnt; + unsigned long CSRBaseAddress; + VOID (*writel_api)(unsigned int value, void *addr,struct mt76_queue *q); + INT32 (*readl_api)(void *addr, struct mt76_queue *q); + struct mt76_queue_regs __iomem *regs_phy0 ; + struct mt76_queue_regs __iomem *regs_phy1 ; + UINT32 wpdma_base_woe; + UINT32 wed_int_msk; + UINT32 irqmask; + UINT32 intr_return; + BOOLEAN wed_running; + UINT32 ring_rx_val; + UINT32 ring_rx_index; + UINT32 pAd_index; + VOID *OS_Cookie; +}; +#define TRUE 1 +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma0_tx_coherent_int_sts_MASK 0x00800000 // host_dma0_tx_coherent_int_sts[23] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma0_tx_coherent_int_sts_MASK 0x00800000 // host_dma0_tx_coherent_int_sts[23] +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_tx_done_int_sts_16_MASK 0x04000000 // host_dma1_tx_done_int_sts_16[26] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_done_int_sts_16_MASK 0x04000000 // host_dma1_tx_done_int_sts_16[26] +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_tx_coherent_int_sts_MASK 0x00200000 // host_dma1_tx_coherent_int_sts[21] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_coherent_int_sts_MASK 0x00200000 // host_dma1_tx_coherent_int_sts[21] +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma0_rx_coherent_int_sts_MASK 0x00400000 // host_dma0_rx_coherent_int_sts[22] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma0_rx_coherent_int_sts_MASK 0x00400000 // host_dma0_rx_coherent_int_sts[22] +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_rx_coherent_int_sts_MASK 0x00100000 // host_dma1_rx_coherent_int_sts[20] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_rx_coherent_int_sts_MASK 0x00100000 // host_dma1_rx_coherent_int_sts[20] +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_tx_done_int_sts_17_MASK 0x08000000 // host_dma1_tx_done_int_sts_17[27] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_done_int_sts_17_MASK 0x08000000 // host_dma1_tx_done_int_sts_17[27] +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_tx_done_int_sts_20_MASK 0x00008000 // host_dma1_tx_done_int_sts_20[15] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_tx_done_int_sts_20_MASK 0x00008000 // host_dma1_tx_done_int_sts_20[15] +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma0_rx_done_int_sts_0_MASK 0x00010000 // host_dma0_rx_done_int_sts_0[16] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma0_rx_don_int_sts_0_MASK 0x00010000 // host_dma0_rx_don_int_sts_0[16] +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma0_rx_done_int_sts_1_MASK 0x00020000 // host_dma0_rx_done_int_sts_1[17] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma0_rx_don_int_sts_1_MASK 0x00020000 // host_dma0_rx_don_int_sts_1[17] +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_rx_done_int_sts_0_MASK 0x00000001 // host_dma1_rx_done_int_sts_0[0] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_rx_done_int_sts_0_MASK 0x00000001 // host_dma1_rx_done_int_sts_0[0] +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_rx_done_int_sts_1_MASK 0x00000002 // host_dma1_rx_done_int_sts_1[1] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_rx_done_int_sts_1_MASK 0x00000002 // host_dma1_rx_done_int_sts_1[1] +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_rx_done_int_sts_2_MASK 0x00000004 // host_dma1_rx_done_int_sts_2[2] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_rx_done_int_sts_2_MASK 0x00000004 // host_dma1_rx_done_int_sts_2[2] +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_mcu2host_sw_int_sts_MASK 0x20000000 // host_dma1_mcu2host_sw_int_sts[29] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_mcu2host_sw_int_sts_MASK 0x20000000 // host_dma1_mcu2host_sw_int_sts[29] +#define WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_subsys_int_sts_MASK 0x10000000 // host_dma1_subsys_int_sts[28] +#define WF_WFDMA_EXT_WRAP_CSR_WFDMA_HOST_INT_STA_host_dma1_subsys_int_sts_MASK 0x10000000 // host_dma1_subsys_int_sts[28] + +#define MT_INT_DMA0_TX_COHE WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma0_tx_coherent_int_sts_MASK +#define MT_INT_DMA1_TX_COHE WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_tx_coherent_int_sts_MASK +#define MT_INT_DMA0_RX_COHE WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma0_rx_coherent_int_sts_MASK +#define MT_INT_DMA1_RX_COHE WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_rx_coherent_int_sts_MASK + +#define MT_INT_DMA1_T16_DONE WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_tx_done_int_sts_16_MASK +#define MT_INT_DMA1_T17_DONE WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_tx_done_int_sts_17_MASK +#define MT_INT_DMA1_T20_DONE WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_tx_done_int_sts_20_MASK +#define MT_INT_DMA0_R0_DONE WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma0_rx_done_int_sts_0_MASK +#define MT_INT_DMA0_R1_DONE WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma0_rx_done_int_sts_1_MASK +#define MT_INT_DMA1_R0_DONE WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_rx_done_int_sts_0_MASK +#define MT_INT_DMA1_R1_DONE WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_rx_done_int_sts_1_MASK +#define MT_INT_DMA1_R2_DONE WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_rx_done_int_sts_2_MASK +#define MT_INT_MCU2HOST_SW_INT_STS WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_mcu2host_sw_int_sts_MASK +#define MT_INT_SUBSYS_INT_STS WF_WFDMA_EXT_WRAP_CSR_WED_HOST_INT_STA_host_dma1_subsys_int_sts_MASK + +#define MT_INT_TxCoherent (MT_INT_DMA0_TX_COHE | MT_INT_DMA1_TX_COHE) +#define MT_INT_RxCoherent (MT_INT_DMA0_RX_COHE | MT_INT_DMA1_RX_COHE) +#define MT_INT_CoherentInt (MT_INT_TxCoherent | MT_INT_RxCoherent) + +#define MT_INT_RX_DATA (MT_INT_DMA0_R0_DONE | MT_INT_DMA0_R1_DONE) +#define MT_INT_RX_CMD (MT_INT_DMA1_R0_DONE | MT_INT_DMA1_R1_DONE | MT_INT_DMA1_R2_DONE) +#define MT_INT_RX_W (MT_INT_RX_DATA | MT_INT_RX_CMD) + +#define TX_RES_NUM 2 +#define MT7915_TX_RING_SIZE 2048 +#define MT7915_HW_TOKEN_SIZE_WOE 7168 +#define WED_REG_BASE 0 +#define WED_TX0_CTRL0 (WED_REG_BASE + 0x00000300) +#define WED_TX0_CTRL1 (WED_REG_BASE + 0x00000304) +#define WED_TX0_CTRL2 (WED_REG_BASE + 0x00000308) +#define WED_TX0_CTRL3 (WED_REG_BASE + 0x0000030C) +#define WED_TX1_CTRL0 (WED_REG_BASE + 0x00000310) +#define WED_TX1_CTRL1 (WED_REG_BASE + 0x00000314) +#define WED_TX1_CTRL2 (WED_REG_BASE + 0x00000318) +#define WED_TX1_CTRL3 (WED_REG_BASE + 0x0000031C) +extern unsigned int wed_base_addr; +extern unsigned int wed_base_addr_1; +extern int woe_enable(void); +extern void set_woe_enable(int enable); +extern int mt_wlan_hook_call(unsigned short hook, void *ad, void *priv); +typedef enum { + WLAN_HOOK_FIRST = 0, + WLAN_HOOK_HIF_INIT = 0, + WLAN_HOOK_HIF_EXIT, + WLAN_HOOK_PEER_LINKUP, + WLAN_HOOK_PEER_LINKDOWN, + WLAN_HOOK_TX, + WLAN_HOOK_RX, + WLAN_HOOK_SYS_UP, + WLAN_HOOK_SYS_DOWN, + WLAN_HOOK_ISR, + WLAN_HOOK_DMA_SET, + WLAN_HOOK_SER, + WLAN_HOOK_SUSPEND, + WLAN_HOOK_RESUME, + WLAN_HOOK_UPDATE, + WLAN_HOOK_IRQ_GET, + WLAN_HOOK_RING_RX_UP, + WLAN_HOOK_END +} WLAN_HOOK_PT; +extern void writel_mt76(unsigned int value, void *addr,struct mt76_queue *q); +extern void writel_mt76(unsigned int value, void *addr,struct mt76_queue *q); + +typedef struct pci_dev *PPCI_DEV; +typedef struct _OS_RSTRUC { + UCHAR *pContent; /* pointer to real structure content */ +} OS_RSTRUC; + +typedef OS_RSTRUC RTMP_NET_TASK_STRUCT; +#define RTMP_OS_PID ULONG /* value or pointer */ +typedef enum _RTMP_INF_TYPE_ { + RTMP_DEV_INF_UNKNOWN = 0, + RTMP_DEV_INF_PCI = 1, + RTMP_DEV_INF_USB = 2, + RTMP_DEV_INF_RBUS = 4, + RTMP_DEV_INF_PCIE = 5, + RTMP_DEV_INF_SDIO = 6, +} RTMP_INF_TYPE; +#define ra_dma_addr_t unsigned long long +typedef ra_dma_addr_t NDIS_PHYSICAL_ADDRESS; +typedef void *PNDIS_PACKET; +typedef struct _RTMP_DMABUF { + ULONG AllocSize; + PVOID AllocVa; + NDIS_PHYSICAL_ADDRESS AllocPa; +} RTMP_DMABUF, *PRTMP_DMABUF; +struct os_cookie +{ +//#ifdef RTMP_MAC_PCI + PPCI_DEV pci_dev; + PPCI_DEV parent_pci_dev; + USHORT DeviceID; +//#endif /* RTMP_MAC_PCI */ + struct device *pDev; + UINT32 pAd_va; +#if defined(RTMP_MAC_PCI) || defined(RTMP_MAC_USB) +#ifdef UAPSD_SUPPORT + RTMP_NET_TASK_STRUCT uapsd_eosp_sent_task; +#endif /* UAPSD_SUPPORT */ +#ifdef CONFIG_AP_SUPPORT +#ifdef CARRIER_DETECTION_SUPPORT + RTMP_NET_TASK_STRUCT carrier_sense_task; +#endif /* CARRIER_DETECTION_SUPPORT */ +#endif /* CONFIG_AP_SUPPORT */ +#endif + RTMP_OS_PID apd_pid; /*802.1x daemon pid */ + unsigned long apd_pid_nr; +#ifdef CONFIG_AP_SUPPORT +#ifdef IAPP_SUPPORT + /* RT_SIGNAL_STRUC RTSignal; */ + RTMP_OS_PID IappPid; /*IAPP daemon pid */ + unsigned long IappPid_nr; +#endif /* IAPP_SUPPORT */ +#endif /* CONFIG_AP_SUPPORT */ + INT ioctl_if_type; + INT ioctl_if; + struct _SECURITY_CONFIG *pSecConfig; +#ifdef FW_DUMP_SUPPORT + struct proc_dir_entry *proc_fwdump_dir; + struct proc_dir_entry *proc_fwdump_file; + CHAR fwdump_dir_name[11]; +#endif +}; +typedef struct os_cookie *POS_COOKIE; +typedef struct _RTMP_DMACB { + ULONG AllocSize; /* Control block size */ + PVOID AllocVa; /* Control block virtual address */ + NDIS_PHYSICAL_ADDRESS AllocPa; /* Control block physical address */ + PNDIS_PACKET pNdisPacket; + PNDIS_PACKET pNextNdisPacket; + NDIS_PHYSICAL_ADDRESS PacketPa; + RTMP_DMABUF DmaBuf; +} RTMP_DMACB, *PRTMP_DMACB ____cacheline_aligned; +typedef spinlock_t OS_NDIS_SPIN_LOCK; +#define NDIS_SPIN_LOCK OS_NDIS_SPIN_LOCK +typedef unsigned char UINT8; +typedef unsigned short UINT16; + +#ifdef DBDC_MODE +#define DBDC_BAND_NUM 2 +#else +#define DBDC_BAND_NUM 1 +#endif /* DBDC_MODE */ +enum PACKET_TYPE { + TX_DATA, + TX_DATA_HIGH_PRIO, + TX_MGMT, + TX_ALTX, + TX_CMD, + TX_FW_DL, + TX_DATA_PS, + RX_PPE_VALID, + PACKET_TYPE_NUM, +}; +#define WMM_QUE_NUM 4 +enum buf_alloc_type { + DYNAMIC_PAGE_ALLOC, + DYNAMIC_SLAB_ALLOC, + PRE_SLAB_ALLOC, + DYNAMIC_PAGE_ALLOC_DEBUG, + PKT_ALLOC_TYPE_NUMS +}; +enum { + GET_PKT_DDONE, + GET_PKT_IO, + GET_PKT_METHOD_NUMS +}; +#if 0 +#define MT_WFDMA_HOST_CONFIG_WED BIT(1) +#define MT_QFLAG_WED_RING GENMASK(1, 0) +#define MT_QFLAG_WED_TYPE GENMASK(3, 2) +#define MT_QFLAG_WED BIT(4) +#define __MT_WED_Q(_type, _n) (MT_QFLAG_WED | \ + FIELD_PREP(MT_QFLAG_WED_TYPE, _type) | \ + FIELD_PREP(MT_QFLAG_WED_RING, _n)) + +#define MT_WED_Q_TX(_n) __MT_WED_Q(MT76_WED_Q_TX, _n) +#define MT_WED_Q_TXFREE __MT_WED_Q(MT76_WED_Q_TXFREE, 0) +enum mt76_wed_type { + MT76_WED_Q_TX, + MT76_WED_Q_TXFREE, +}; +#endif +#define TX_QUEUE0_INDEX 18 +#define TX_QUEUE1_INDEX 19 +#define MT_RXQ_MCU_WA_RING_BASE 0xd7400 +extern struct woe_need pAd; +extern struct woe_need pAd_1; +struct wlan_tx_info_woe { + unsigned char *pkt; + unsigned int bssidx; + unsigned int wcid; + unsigned int ringidx; +}; + +static inline void +mtk_wed_irq_set_mask_woe(struct mt76_dev *dev,unsigned int mask) +{ +#ifdef CONFIG_SOC_WOE + if(dev->slot_id == 0) + { + if(!(pAd.wed_running)) + return; + pAd.wed_int_msk = mask; + mt_wlan_hook_call(WLAN_HOOK_UPDATE, &pAd, NULL); + } + else +#endif + { + if(!(pAd_1.wed_running)) + return; + pAd_1.wed_int_msk = mask; + mt_wlan_hook_call(WLAN_HOOK_UPDATE, &pAd_1, NULL); + } +} + +static inline INT os_alloc_mem( + VOID *pAd, + UCHAR **mem, + ULONG size) +{ + *mem = (PUCHAR) kmalloc(size, GFP_ATOMIC); + + if (*mem) { + return NDIS_STATUS_SUCCESS; + } else + return NDIS_STATUS_FAILURE; +} + + +static inline void woe_start(struct pci_dev *pdev, struct mt76_dev *mdev, unsigned long csr_addr, u32 wpdma_base_woe) +{ + struct os_cookie *handle = NULL; + struct woe_need pAd_woe; +#ifdef CONFIG_SOC_WOE + if (pdev->bus) + mdev->slot_id = (pdev->bus->self->devfn >> 3) & 0x1f; + else + mdev->slot_id = 1; + if(mdev->slot_id == 0) + pAd_woe.pAd_index = WHNAT_0; + else +#endif + pAd_woe.pAd_index = WHNAT_1; + /*modify to get from pcie init*/ + pAd_woe.ChipID = CHIP_ID_WOE; + /*modify get from wifi config*/ + pAd_woe.whnat_en = TRUE; + /*get slot id*/ + os_alloc_mem(NULL, (UCHAR **)&handle, sizeof(struct os_cookie)); + if (handle == NULL) { + printk("%s:%d handle alloc fail !!!\n",__func__,__LINE__); + } + memset(handle, 0, sizeof(struct os_cookie)); + ((POS_COOKIE)handle)->pci_dev = pdev; + ((POS_COOKIE)handle)->pDev = &(pdev->dev); + pAd_woe.OS_Cookie = handle; + + /*tx res num & tx ring size*/ + pAd_woe.tx_res_num = TX_RES_NUM; + pAd_woe.mt76_queue_info.ndesc = MT7915_TX_RING_SIZE; + /*int_enable_mask config wifi chip*/ + pAd_woe.int_enable_mask = MT_INT_CoherentInt | MT_INT_DMA1_T16_DONE | + MT_INT_DMA1_T17_DONE | MT_INT_DMA1_T20_DONE | MT_INT_RX_W; + pAd_woe.int_enable_mask |= MT_INT_MCU2HOST_SW_INT_STS | MT_INT_SUBSYS_INT_STS; + /*token number */ + pAd_woe.token_tx_cnt = MT7915_TOKEN_SIZE; + pAd_woe.hw_tx_token_cnt = MT7915_HW_TOKEN_SIZE_WOE; + pAd_woe.CSRBaseAddress = csr_addr; + //MT_WED_TX_RING_BASE+dev->mmio.regs + pAd_woe.wpdma_base_woe = wpdma_base_woe; + if(pAd_woe.pAd_index == WHNAT_0) + { + memcpy(&pAd, &pAd_woe, sizeof(pAd_woe)); + mt_wlan_hook_call(WLAN_HOOK_SYS_UP, &pAd, NULL); + } + else + { + memcpy(&pAd_1, &pAd_woe, sizeof(pAd_woe)); + mt_wlan_hook_call(WLAN_HOOK_SYS_UP, &pAd_1, NULL); + } +} + + static inline void mtk_wed_irq_set_mask(struct mt7915_dev *dev, unsigned int mask) + { +#ifdef CONFIG_SOC_WOE + if(dev->mt76.slot_id == 0) + { + if(!(pAd.wed_running)) + return; + pAd.wed_int_msk = mask; + mt_wlan_hook_call(WLAN_HOOK_UPDATE, &pAd, NULL); + } + else +#endif + { + if(!(pAd_1.wed_running)) + return; + pAd_1.wed_int_msk = mask; + mt_wlan_hook_call(WLAN_HOOK_UPDATE, &pAd_1, NULL); + } + } + +static inline u32 +mtk_wed_irq_get(struct mt7915_dev *dev, u32 mask) +{ +#ifdef CONFIG_SOC_WOE + if(dev->mt76.slot_id == 0) + { + pAd.irqmask = mask; + mt_wlan_hook_call(WLAN_HOOK_IRQ_GET, &pAd, NULL); + return pAd.intr_return; + } + else +#endif + { + pAd_1.irqmask = mask; + mt_wlan_hook_call(WLAN_HOOK_IRQ_GET, &pAd_1, NULL); + return pAd_1.intr_return; + } +} + +static inline void +mt76_dma_sync_idx_woe(struct mt76_dev *dev, struct mt76_queue *q) +{ +#ifdef CONFIG_SOC_WOE + if(dev->slot_id == 0) + { + pAd.writel_api(q->desc_dma, &q->regs->desc_base, q); + pAd.writel_api(q->ndesc, &q->regs->ring_size, q); + q->head = pAd.readl_api(&q->regs->dma_idx, q); + q->tail = q->head; + } + else +#endif + { + pAd_1.writel_api(q->desc_dma, &q->regs->desc_base, q); + pAd_1.writel_api(q->ndesc, &q->regs->ring_size, q); + q->head = pAd_1.readl_api(&q->regs->dma_idx, q); + q->tail = q->head; + } +} +static inline void +mt76_dma_queue_reset_woe(struct mt76_dev *dev, struct mt76_queue *q) +{ + int i; + if (!q || !q->ndesc) + return; + /* clear descriptors */ + for (i = 0; i < q->ndesc; i++) + q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); +#ifdef CONFIG_SOC_WOE + if(dev->slot_id == 0) + { + pAd.writel_api(0, &q->regs->cpu_idx, q); + pAd.writel_api(0, &q->regs->dma_idx, q); + } + else +#endif + { + pAd_1.writel_api(0, &q->regs->cpu_idx, q); + pAd_1.writel_api(0, &q->regs->dma_idx, q); + } + mt76_dma_sync_idx_woe(dev, q); +} +//int mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q); +static inline int +mtk_wed_device_txfree_ring_setup(struct mt76_dev *dev, void __iomem *regs) +{ + int i; + u32 val; + for (i = 0; i < 12; i += 4) { + val = readl(regs + i); +#ifdef CONFIG_SOC_WOE + if(dev->slot_id == 0) + { + pAd.ring_rx_val = val; + pAd.ring_rx_index = i; + mt_wlan_hook_call(WLAN_HOOK_RING_RX_UP, &pAd, NULL); + } + else +#endif + { + pAd_1.ring_rx_val = val; + pAd_1.ring_rx_index = i; + mt_wlan_hook_call(WLAN_HOOK_RING_RX_UP, &pAd_1, NULL); + } + } + return 0; +} + +#if 0 +static inline int +mt76_dma_wed_setup(struct mt76_dev *dev, struct mt76_queue *q, bool reset) +{ + //struct mtk_wed_device *wed = &dev->mmio.wed; + int ret, type, ring, i; + u8 flags = q->flags; + type = FIELD_GET(MT_QFLAG_WED_TYPE, q->flags); + ring = FIELD_GET(MT_QFLAG_WED_RING, q->flags); + switch (type) { + case MT76_WED_Q_TXFREE: + /* WED txfree queue needs ring to be initialized before setup */ + q->flags = 0; + for (i = 0; i < q->ndesc; i++) + q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); + writel(0, &q->regs->cpu_idx); + writel(0, &q->regs->dma_idx); + writel(q->desc_dma, &q->regs->desc_base); + writel(q->ndesc, &q->regs->ring_size); + q->head = readl(&q->regs->dma_idx); + q->tail = q->head; + mt76_dma_rx_fill(dev, q); + q->flags = flags; + q->wed_regs = WED_RX1_CTRL0; + ret = mtk_wed_device_txfree_ring_setup(dev, q->regs); + break; + default: + ret = 0; + } + + return ret; +} +#endif +static inline int woe_read_1(struct mt76_dev *dev, struct mt76_queue *q) +{ + int val; + if(q->flags == 1) + { +#ifdef CONFIG_SOC_WOE + if(dev->slot_id == 0) + val = readl((void *)(wed_base_addr + q->wed_regs + 12)); + else +#endif + val = readl((void *)(wed_base_addr_1 + q->wed_regs + 12)); + } + else + val = readl(&q->regs->dma_idx); + return val; +} +#endif \ No newline at end of file diff -uNr old/mt7915/dma.c new/mt7915/dma.c --- old/mt7915/dma.c 2023-05-08 12:34:37.429919000 +0800 +++ new/mt7915/dma.c 2023-05-08 13:38:35.987648000 +0800 @@ -5,12 +5,15 @@ #include "../dma.h" #include "mac.h" #include +#ifdef CONFIG_SOC_WOE +#include "../mt76_woe.h" +#endif static int mt7915_init_tx_queues(struct mt7915_phy *phy, int idx, int n_desc, int ring_base) { struct mt7915_dev *dev = phy->dev; - +#if 0 if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) { if (is_mt7986(&dev->mt76)) ring_base += MT_TXQ_ID(0) * MT_RING_SIZE; @@ -19,7 +22,7 @@ idx -= MT_TXQ_ID(0); } - +#endif return mt76_connac_init_tx_queues(phy->mt76, idx, n_desc, ring_base, MT_WED_Q_TX(idx)); } @@ -51,39 +54,25 @@ #define TXQ_CONFIG(q, wfdma, int, id) Q_CONFIG(__TXQ(q), (wfdma), (int), (id)) if (is_mt7915(&dev->mt76)) { - RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, - MT7915_RXQ_BAND0); - RXQ_CONFIG(MT_RXQ_MCU, WFDMA1, MT_INT_RX_DONE_WM, - MT7915_RXQ_MCU_WM); - RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA1, MT_INT_RX_DONE_WA, - MT7915_RXQ_MCU_WA); - RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1, - MT7915_RXQ_BAND1); - RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA1, MT_INT_RX_DONE_WA_EXT, - MT7915_RXQ_MCU_WA_EXT); - RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA1, MT_INT_RX_DONE_WA_MAIN, - MT7915_RXQ_MCU_WA); + RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0, MT7915_RXQ_BAND0); + RXQ_CONFIG(MT_RXQ_MCU, WFDMA1, MT_INT_RX_DONE_WM, MT7915_RXQ_MCU_WM); + RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA1, MT_INT_RX_DONE_WA, MT7915_RXQ_MCU_WA); + RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1, MT7915_RXQ_BAND1); + RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA1, MT_INT_RX_DONE_WA_EXT, MT7915_RXQ_MCU_WA_EXT); + RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA1, MT_INT_RX_DONE_WA_MAIN, MT7915_RXQ_MCU_WA); TXQ_CONFIG(0, WFDMA1, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0); TXQ_CONFIG(1, WFDMA1, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1); - MCUQ_CONFIG(MT_MCUQ_WM, WFDMA1, MT_INT_TX_DONE_MCU_WM, - MT7915_TXQ_MCU_WM); - MCUQ_CONFIG(MT_MCUQ_WA, WFDMA1, MT_INT_TX_DONE_MCU_WA, - MT7915_TXQ_MCU_WA); - MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA1, MT_INT_TX_DONE_FWDL, - MT7915_TXQ_FWDL); + MCUQ_CONFIG(MT_MCUQ_WM, WFDMA1, MT_INT_TX_DONE_MCU_WM, MT7915_TXQ_MCU_WM); + MCUQ_CONFIG(MT_MCUQ_WA, WFDMA1, MT_INT_TX_DONE_MCU_WA, MT7915_TXQ_MCU_WA); + MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA1, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL); } else { - RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, - MT7916_RXQ_MCU_WM); - RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT_MT7916, - MT7916_RXQ_MCU_WA_EXT); - MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, - MT7915_TXQ_MCU_WM); - MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA_MT7916, - MT7915_TXQ_MCU_WA); - MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, - MT7915_TXQ_FWDL); - - if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) { + RXQ_CONFIG(MT_RXQ_MCU, WFDMA0, MT_INT_RX_DONE_WM, MT7916_RXQ_MCU_WM); + RXQ_CONFIG(MT_RXQ_BAND1_WA, WFDMA0, MT_INT_RX_DONE_WA_EXT_MT7916, MT7916_RXQ_MCU_WA_EXT); + MCUQ_CONFIG(MT_MCUQ_WM, WFDMA0, MT_INT_TX_DONE_MCU_WM, MT7915_TXQ_MCU_WM); + MCUQ_CONFIG(MT_MCUQ_WA, WFDMA0, MT_INT_TX_DONE_MCU_WA_MT7916, MT7915_TXQ_MCU_WA); + MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, MT7915_TXQ_FWDL); +#ifdef CONFIG_SOC_WOE + if (is_mt7916(&dev->mt76) && woe_enable()) { RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_WED_RX_DONE_BAND0_MT7916, MT7916_RXQ_BAND0); RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MT7916, @@ -93,26 +82,21 @@ MT7916_RXQ_BAND1); else RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_WED_RX_DONE_BAND1_MT7916, - MT7916_RXQ_BAND1); + MT7916_RXQ_BAND1); RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_WED_RX_DONE_WA_MAIN_MT7916, MT7916_RXQ_MCU_WA_MAIN); - TXQ_CONFIG(0, WFDMA0, MT_INT_WED_TX_DONE_BAND0, - MT7915_TXQ_BAND0); - TXQ_CONFIG(1, WFDMA0, MT_INT_WED_TX_DONE_BAND1, - MT7915_TXQ_BAND1); - } else { - RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0_MT7916, - MT7916_RXQ_BAND0); - RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, - MT7916_RXQ_MCU_WA); - RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916, - MT7916_RXQ_BAND1); + TXQ_CONFIG(0, WFDMA0, MT_INT_WED_TX_DONE_BAND0, MT7915_TXQ_BAND0); + TXQ_CONFIG(1, WFDMA0, MT_INT_WED_TX_DONE_BAND1, MT7915_TXQ_BAND1); + } else +#endif + { + RXQ_CONFIG(MT_RXQ_MAIN, WFDMA0, MT_INT_RX_DONE_BAND0_MT7916, MT7916_RXQ_BAND0); + RXQ_CONFIG(MT_RXQ_MCU_WA, WFDMA0, MT_INT_RX_DONE_WA, MT7916_RXQ_MCU_WA); + RXQ_CONFIG(MT_RXQ_BAND1, WFDMA0, MT_INT_RX_DONE_BAND1_MT7916, MT7916_RXQ_BAND1); RXQ_CONFIG(MT_RXQ_MAIN_WA, WFDMA0, MT_INT_RX_DONE_WA_MAIN_MT7916, MT7916_RXQ_MCU_WA_MAIN); - TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, - MT7915_TXQ_BAND0); - TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, - MT7915_TXQ_BAND1); + TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7915_TXQ_BAND0); + TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7915_TXQ_BAND1); } } } @@ -357,13 +341,12 @@ irq_mask = MT_INT_RX_DONE_MCU | MT_INT_TX_DONE_MCU | MT_INT_MCU_CMD; - if (!dev->phy.mt76->band_idx) irq_mask |= MT_INT_BAND0_RX_DONE; if (dev->dbdc_support || dev->phy.mt76->band_idx) irq_mask |= MT_INT_BAND1_RX_DONE; - +#if 0 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { u32 wed_irq_mask = irq_mask; int ret; @@ -380,11 +363,44 @@ mtk_wed_device_start(&dev->mt76.mmio.wed, wed_irq_mask); } - +#endif +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + { + u32 wed_irq_mask = irq_mask; + wed_irq_mask |= MT_INT_TX_DONE_BAND0 | MT_INT_TX_DONE_BAND1; + mt76_wr(dev, MT_INT_WED_MASK_CSR, wed_irq_mask); + if(mdev->slot_id == 0) + { + pAd.wed_int_msk = wed_irq_mask; + mt_wlan_hook_call(WLAN_HOOK_HIF_INIT, &pAd, NULL); + } + else + { + pAd_1.wed_int_msk = wed_irq_mask; + mt_wlan_hook_call(WLAN_HOOK_HIF_INIT, &pAd_1, NULL); + } + } +#endif mt7915_irq_enable(dev, irq_mask); return 0; } +#define MT_WFDMA0_GLO_CFG_DUMMY_REG BIT(10) + +#define MT_WFDMA0_CFG_EXT MT_WFDMA0(0x2b4) +#define MT_WFDMA0_EXT_TX_FCTRL_MODE BIT(28) + +#define MT_WFDMA0_CTXD_CFG MT_WFDMA0(0x2bc) +#define MT_WFDMA0_BAND0_CTXD_EN BIT(0) +#define MT_WFDMA0_BAND0_CTXD_RING_IDX GENMASK(5, 1) +#define MT_WFDMA0_BAND1_CTXD_EN BIT(6) +#define MT_WFDMA0_BAND1_CTXD_RING_IDX GENMASK(11, 7) +#define MT_WFDMA0_CTXD_CASCADE_NUM GENMASK(15, 12) +#define MT_WFDMA0_CTXD_TIMEOUT GENMASK(23, 16) + +#define MT_WFDMA_WED_DLY_INT_TICK MT_WFDMA_EXT_CSR_PHYS(0x38) +#define MT_CBTOP_RESV 0x70010210 int mt7915_dma_init(struct mt7915_dev *dev, struct mt7915_phy *phy2) { @@ -401,7 +417,7 @@ hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); mt7915_dma_disable(dev, true); - +#if 0 if (mtk_wed_device_active(&mdev->mmio.wed)) { if (!is_mt7986(mdev)) { u8 wed_control_rx1 = is_mt7915(mdev) ? 1 : 2; @@ -420,6 +436,42 @@ } else { mt76_clear(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED); } +#endif +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + { + u8 wed_control_rx1 = is_mt7915(mdev) ? 1 : 2; + mt76_set(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED); + mt76_wr(dev, MT_WFDMA_WED_RING_CONTROL, + FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX0, 18) | + FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_TX1, 19) | + FIELD_PREP(MT_WFDMA_WED_RING_CONTROL_RX1, wed_control_rx1)); + if(is_mt7915(mdev)) + mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP, + MT_WFDMA0_EXT0_RXWB_KEEP); + else { + if (mt76_rr(dev, MT_CBTOP_RESV) & 0xff == 2) { + mt76_set(dev, MT_WFDMA0_GLO_CFG, MT_WFDMA0_GLO_CFG_DUMMY_REG); + mt76_set(dev, MT_WFDMA0_CTXD_CFG, FIELD_PREP(MT_WFDMA0_CTXD_TIMEOUT, 0xa)); + } else { + mt76_set(dev, MT_WFDMA0_CTXD_CFG, FIELD_PREP(MT_WFDMA0_CTXD_TIMEOUT, 0xff)); + mt76_wr(dev, MT_WFDMA_WED_DLY_INT_TICK, 0xffff); + } + + mt76_clear(dev, MT_WFDMA0_CTXD_CFG, MT_WFDMA0_CTXD_CASCADE_NUM); + + mt76_set(dev, MT_WFDMA0_CTXD_CFG, + FIELD_PREP(MT_WFDMA0_BAND0_CTXD_RING_IDX, 18) | + FIELD_PREP(MT_WFDMA0_BAND1_CTXD_RING_IDX, 19) | + MT_WFDMA0_BAND0_CTXD_EN | MT_WFDMA0_BAND1_CTXD_EN); + + mt76_set(dev, MT_WFDMA0_CFG_EXT, MT_WFDMA0_EXT_TX_FCTRL_MODE); + } + } + else +#endif + mt76_clear(dev, MT_WFDMA_HOST_CONFIG, MT_WFDMA_HOST_CONFIG_WED); + /* init tx queue */ ret = mt7915_init_tx_queues(&dev->phy, @@ -470,7 +522,7 @@ MT_RXQ_RING_BASE(MT_RXQ_MCU)); if (ret) return ret; - +#if 0 /* event from WA */ if (mtk_wed_device_active(&mdev->mmio.wed) && is_mt7915(mdev)) { wa_rx_base = MT_WED_RX_RING_BASE; @@ -480,6 +532,23 @@ wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MCU_WA); wa_rx_idx = MT_RXQ_ID(MT_RXQ_MCU_WA); } +#endif +#ifdef CONFIG_SOC_WOE + if(is_mt7915(mdev) && woe_enable()) + { + wa_rx_base = MT_RXQ_MCU_WA_RING_BASE; + wa_rx_idx = MT7915_RXQ_MCU_WA; + dev->mt76.q_rx[MT_RXQ_MCU_WA].flags = MT_WED_Q_TXFREE; + } + else + { + wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MCU_WA); + wa_rx_idx = MT_RXQ_ID(MT_RXQ_MCU_WA); + } +#else + wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MCU_WA); + wa_rx_idx = MT_RXQ_ID(MT_RXQ_MCU_WA); +#endif ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA], wa_rx_idx, MT7915_RX_MCU_RING_SIZE, MT_RX_BUF_SIZE, wa_rx_base); @@ -488,12 +557,13 @@ /* rx data queue for band0 */ if (!dev->phy.mt76->band_idx) { +#if 0 if (mtk_wed_device_active(&mdev->mmio.wed) && mtk_wed_get_rx_capa(&mdev->mmio.wed)) { dev->mt76.q_rx[MT_RXQ_MAIN].flags = MT_WED_Q_RX(MT7915_RXQ_BAND0); } - +#endif ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN], MT_RXQ_ID(MT_RXQ_MAIN), MT7915_RX_RING_SIZE, @@ -507,7 +577,17 @@ if (!is_mt7915(mdev)) { wa_rx_base = MT_RXQ_RING_BASE(MT_RXQ_MAIN_WA); wa_rx_idx = MT_RXQ_ID(MT_RXQ_MAIN_WA); - +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + { + mdev->q_rx[MT_RXQ_MAIN_WA].flags = MT_WED_Q_TXFREE; + if (is_mt7916(mdev)) { + wa_rx_base = MT_WED_RX_RING_BASE; + wa_rx_idx = MT7915_RXQ_MCU_WA; + } + } +#endif +#if 0 if (mtk_wed_device_active(&mdev->mmio.wed)) { mdev->q_rx[MT_RXQ_MAIN_WA].flags = MT_WED_Q_TXFREE; if (is_mt7916(mdev)) { @@ -515,7 +595,7 @@ wa_rx_idx = MT7915_RXQ_MCU_WA; } } - +#endif ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA], wa_rx_idx, MT7915_RX_MCU_RING_SIZE, MT_RX_BUF_SIZE, wa_rx_base); @@ -524,12 +604,13 @@ } if (dev->dbdc_support || dev->phy.mt76->band_idx) { +#if 0 if (mtk_wed_device_active(&mdev->mmio.wed) && mtk_wed_get_rx_capa(&mdev->mmio.wed)) { dev->mt76.q_rx[MT_RXQ_BAND1].flags = MT_WED_Q_RX(MT7915_RXQ_BAND1); } - +#endif /* rx data queue for band1 */ ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1], MT_RXQ_ID(MT_RXQ_BAND1), @@ -565,7 +646,9 @@ int mt7915_dma_reset(struct mt7915_dev *dev, bool force) { struct mt76_phy *mphy_ext = dev->mt76.phys[MT_BAND1]; +#if 0 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; +#endif int i; /* clean up hw queues */ @@ -584,13 +667,14 @@ /* reset wfsys */ if (force) mt7915_wfsys_reset(dev); - +#if 0 + /* disable wfdma */ if (mtk_wed_device_active(&dev->mt76.mmio.wed)) mtk_wed_device_dma_reset(&dev->mt76.mmio.wed); +#endif mt7915_dma_disable(dev, force); - +#if 0 /* set wifi reset done, wait FE reset */ -#ifdef MT76_MTK_WOE if (mtk_wed_device_active(wed) && atomic_read(&wed->fe_reset)) { atomic_set(&wed->fe_reset, 0); rtnl_lock(); @@ -604,14 +688,19 @@ mt76_queue_reset(dev, dev->mphy.q_tx[i]); if (mphy_ext) { mt76_queue_reset(dev, mphy_ext->q_tx[i]); +#if 0 if (mtk_wed_device_active(wed)) mt76_dma_wed_setup(&dev->mt76, mphy_ext->q_tx[i], true); + +#endif } +#if 0 if (mtk_wed_device_active(wed)) mt76_dma_wed_setup(&dev->mt76, dev->mphy.q_tx[i], true); +#endif } for (i = 0; i < __MT_MCUQ_MAX; i++) @@ -626,11 +715,11 @@ mt76_for_each_q_rx(&dev->mt76, i) mt76_queue_rx_reset(dev, i); - +#if 0 if(mtk_wed_device_active(wed) && is_mt7915(&dev->mt76)) mt76_rmw(dev, MT_WFDMA0_EXT0_CFG, MT_WFDMA0_EXT0_RXWB_KEEP, MT_WFDMA0_EXT0_RXWB_KEEP); - +#endif mt7915_dma_enable(dev); return 0; diff -uNr old/mt7915/mac.c new/mt7915/mac.c --- old/mt7915/mac.c 2023-05-08 12:34:37.447928000 +0800 +++ new/mt7915/mac.c 2023-05-08 10:52:59.405365000 +0800 @@ -9,6 +9,9 @@ #include "mac.h" #include "mcu.h" #include "vendor.h" +#ifdef CONFIG_SOC_WOE +#include "../mt76_woe.h" +#endif #define to_rssi(field, rcpi) ((FIELD_GET(field, rcpi) - 220) / 2) @@ -245,7 +248,7 @@ else mt76_clear(dev, addr, BIT(5)); } - +#if 0 static void mt7915_wed_check_ppe(struct mt7915_dev *dev, struct mt76_queue *q, struct mt7915_sta *msta, struct sk_buff *skb, @@ -273,7 +276,7 @@ FIELD_GET(MT_DMA_PPE_CPU_REASON, info), FIELD_GET(MT_DMA_PPE_ENTRY, info)); } - +#endif static int mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb, enum mt76_rxq_id q, u32 *info) @@ -555,8 +558,10 @@ #endif } else { status->flag |= RX_FLAG_8023; +#if 0 mt7915_wed_check_ppe(dev, &dev->mt76.q_rx[q], msta, skb, *info); +#endif } if (rxv && mode >= MT_PHY_TYPE_HE_SU && !(status->flag & RX_FLAG_8023)) @@ -797,6 +802,10 @@ int id, i, nbuf = tx_info->nbuf - 1; u8 *txwi = (u8 *)txwi_ptr; int pid; +#ifdef CONFIG_SOC_WOE + struct wlan_tx_info_woe tx_info_woe; +#endif + struct mt7915_sta *msta = NULL; if (unlikely(tx_info->skb->len <= ETH_HLEN)) return -EINVAL; @@ -805,7 +814,7 @@ wcid = &dev->mt76.global_wcid; if (sta) { - struct mt7915_sta *msta; + //struct mt7915_sta *msta; msta = (struct mt7915_sta *)sta->drv_priv; @@ -821,6 +830,9 @@ if (ieee80211_is_action(fc) && mgmt->u.action.category == 0xff) return -1; +#ifdef CONFIG_SOC_WOE + tx_info_woe.pkt = (unsigned char *)tx_info->skb; +#endif id = mt76_token_consume(mdev, &t); if (id < 0) @@ -829,6 +841,13 @@ pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb); mt7915_mac_write_txwi(mdev, txwi_ptr, tx_info->skb, wcid, pid, key, qid, 0); +#ifdef CONFIG_SOC_WOE + tx_info_woe.wcid = wcid->idx; + if(msta) + tx_info_woe.ringidx = msta->vif->mt76.band_idx; + else + tx_info_woe.ringidx = 3; +#endif txp = (struct mt76_connac_fw_txp *)(txwi + MT_TXD_SIZE); for (i = 0; i < nbuf; i++) { @@ -850,6 +869,9 @@ struct mt7915_vif *mvif = (struct mt7915_vif *)vif->drv_priv; txp->bss_idx = mvif->mt76.idx; +#ifdef CONFIG_SOC_WOE + tx_info_woe.bssidx = mvif->mt76.idx; +#endif } txp->token = cpu_to_le16(id); @@ -863,6 +885,16 @@ tx_info->buf[1].len = MT_CT_PARSE_LEN; tx_info->buf[1].skip_unmap = true; tx_info->nbuf = MT_CT_DMA_BUF_NUM; + //WLAN_HOOK_CALL(WLAN_HOOK_TX, &pAd, &tx_info_woe); +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + { + if(mdev->slot_id == 0) + mt_wlan_hook_call(WLAN_HOOK_TX, &pAd, &tx_info_woe); + else + mt_wlan_hook_call(WLAN_HOOK_TX, &pAd_1, &tx_info_woe); + } +#endif #ifdef MTK_DEBUG if (dev->dbg.dump_txd) @@ -872,7 +904,7 @@ #endif return 0; } - +#if 0 u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id) { struct mt76_connac_fw_txp *txp = ptr + MT_TXD_SIZE; @@ -895,7 +927,8 @@ return MT_TXD_TXP_BUF_SIZE; } - +#endif +#if 0 void mt7915_wed_trigger_ser(struct mtk_wed_device *wed) { struct mt7915_dev *dev; @@ -907,7 +940,7 @@ return; } - +#endif static void mt7915_tx_check_aggr(struct ieee80211_sta *sta, __le32 *txwi) { @@ -1451,6 +1484,7 @@ struct mt76_phy *ext_phy; struct mt76_dev *mdev = &dev->mt76; int i, ret; + u32 irq_mask; ext_phy = dev->mt76.phys[MT_BAND1]; phy2 = ext_phy ? ext_phy->priv : NULL; @@ -1646,13 +1680,13 @@ /* chip partial reset */ if (!(READ_ONCE(dev->recovery.state) & MT_MCU_CMD_STOP_DMA)) return; - +#if 0 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { mtk_wed_device_stop(&dev->mt76.mmio.wed, true); if (!is_mt7986(&dev->mt76)) mt76_wr(dev, MT_INT_WED_MASK_CSR, 0); } - +#endif ieee80211_stop_queues(mt76_hw(dev)); if (ext_phy) ieee80211_stop_queues(ext_phy->hw); diff -uNr old/mt7915/main.c new/mt7915/main.c --- old/mt7915/main.c 2023-05-08 12:34:37.377911000 +0800 +++ new/mt7915/main.c 2023-05-08 10:55:01.095343000 +0800 @@ -7,6 +7,9 @@ #include #include "mt7915.h" #include "mcu.h" +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD +#include "modules/npu/wifi_mail.h" +#endif static bool mt7915_dev_running(struct mt7915_dev *dev) { @@ -702,12 +705,13 @@ int ret, idx; u32 addr; u8 flags = MT76_WED_DEFAULT; - - if (mtk_wed_device_active(&dev->mt76.mmio.wed) && +#if CONFIG_SOC_WOE + if (woe_enable() && !is_mt7915(&dev->mt76)) { flags = test_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags) ? MT76_WED_WDS_ACTIVE : MT76_WED_ACTIVE; } +#endif idx = __mt76_wcid_alloc(mdev->wcid_mask, MT7915_WTBL_STA, flags); if (idx < 0) @@ -835,7 +839,18 @@ struct mt7915_sta *msta = (struct mt7915_sta *)sta->drv_priv; u16 tid = params->tid; u16 ssn = params->ssn; + u8 band; struct mt76_txq *mtxq; +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + struct mt76_phy *mphy = &dev->mt76.phy; + u16 buf_size =params->buf_size; + u16 index = msta->wcid.idx; + if(dev->dbdc_support) + band = msta->vif->mt76.band_idx; + else + band = mphy->chandef.chan->band; + +#endif int ret = 0; if (!txq) @@ -849,10 +864,18 @@ mt76_rx_aggr_start(&dev->mt76, &msta->wcid, tid, ssn, params->buf_size); ret = mt7915_mcu_add_rx_ba(dev, params, true); +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + if(npu_enable()) + WIFI_MAIL_API_SET_WAIT_BA_WIN_SIZE(band,index,tid,buf_size,ssn); +#endif break; case IEEE80211_AMPDU_RX_STOP: mt76_rx_aggr_stop(&dev->mt76, &msta->wcid, tid); ret = mt7915_mcu_add_rx_ba(dev, params, false); +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + if(npu_enable()) + WIFI_MAIL_API_SET_WAIT_BA_WIN_SIZE(band,index, tid,0,0); +#endif break; case IEEE80211_AMPDU_TX_OPERATIONAL: mtxq->aggr = true; @@ -1099,7 +1122,9 @@ /* offloading flows bypass networking stack, so driver counts and * reports sta statistics via NL80211_STA_INFO when WED is active. */ - if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) { +#if CONFIG_SOC_WOE + //if (mtk_wed_device_active(&phy->dev->mt76.mmio.wed)) { + if (woe_enable()) { sinfo->tx_bytes = msta->wcid.stats.tx_bytes; sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BYTES64); @@ -1111,7 +1136,7 @@ sinfo->tx_retries = msta->wcid.stats.tx_retries; sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_RETRIES); - + #if 0 if (mtk_wed_get_rx_capa(&phy->dev->mt76.mmio.wed)) { sinfo->rx_bytes = msta->wcid.stats.rx_bytes; sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_BYTES64); @@ -1119,8 +1144,9 @@ sinfo->rx_packets = msta->wcid.stats.rx_packets; sinfo->filled |= BIT_ULL(NL80211_STA_INFO_RX_PACKETS); } + #endif } - +#endif sinfo->ack_signal = (s8)msta->ack_signal; sinfo->filled |= BIT_ULL(NL80211_STA_INFO_ACK_SIGNAL); @@ -1191,7 +1217,8 @@ else clear_bit(MT_WCID_FLAG_4ADDR, &msta->wcid.flags); - if (mtk_wed_device_active(&dev->mt76.mmio.wed) && +// if (mtk_wed_device_active(&dev->mt76.mmio.wed) && + if (woe_enable() && !is_mt7915(&dev->mt76)) { mt7915_sta_remove(hw, vif, sta); mt76_sta_pre_rcu_remove(hw, vif, sta); @@ -1558,10 +1585,10 @@ struct mt7915_dev *dev = mt7915_hw_dev(hw); struct mt7915_phy *phy = mt7915_hw_phy(hw); struct mtk_wed_device *wed = &dev->mt76.mmio.wed; - +#if 0 if (!mtk_wed_device_active(wed)) return -ENODEV; - +#endif if (msta->wcid.idx > MT7915_WTBL_STA) return -EIO; @@ -1588,10 +1615,10 @@ { struct mt7915_dev *dev = mt7915_hw_dev(hw); struct mtk_wed_device *wed = &dev->mt76.mmio.wed; - +#if 0 if (!mtk_wed_device_active(wed)) return -ENODEV; - +#endif path->dev = ctx->dev; path->mtk_wdma.wdma_idx = wed->wdma_idx; diff -uNr old/mt7915/mcu.c new/mt7915/mcu.c --- old/mt7915/mcu.c 2023-05-08 12:34:37.382926000 +0800 +++ new/mt7915/mcu.c 2023-05-06 11:47:46.452017000 +0800 @@ -7,6 +7,9 @@ #include "mac.h" #include "eeprom.h" #include +#ifdef CONFIG_SOC_WOE +#include "../mt76_woe.h" +#endif #define fw_name(_dev, name, ...) ({ \ char *_fw; \ @@ -1740,9 +1743,11 @@ return ret; } out: +#if 0 ret = mt76_connac_mcu_sta_wed_update(&dev->mt76, skb); if (ret) return ret; +#endif return mt76_mcu_skb_send_msg(&dev->mt76, skb, MCU_EXT_CMD(STA_REC_UPDATE), true); @@ -2332,10 +2337,16 @@ return mt76_mcu_send_msg(&dev->mt76, MCU_EXT_CMD(RX_AIRTIME_CTRL), &req, sizeof(req), true); } - +#define MTK_WED_REV_ID_MAJIOR GENMASK(7, 0) +#define MTK_WED_REV_ID_MINOR GENMASK(27, 16) +#define MTK_WED_V1 0x001 +extern unsigned int wed_ver_id; int mt7915_mcu_init_firmware(struct mt7915_dev *dev) { int ret; + unsigned short dev_ver = 0; + unsigned short recv_id = 0; + unsigned short ver_tmp = 0; /* force firmware operation mode into normal state, * which should be set before firmware download stage. @@ -2364,7 +2375,7 @@ ret = mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WA, 0); if (ret) return ret; - +#if 0 if (mtk_wed_device_active(&dev->mt76.mmio.wed)) { if (is_mt7915(&dev->mt76) || !mtk_wed_get_rx_capa(&dev->mt76.mmio.wed)) @@ -2385,7 +2396,30 @@ if (ret) return ret; } +#endif +#ifdef CONFIG_SOC_WOE +if(woe_enable()) +{ + dev_ver = FIELD_GET(MTK_WED_REV_ID_MAJIOR, wed_ver_id); + if(dev_ver > MTK_WED_V1) + ver_tmp = FIELD_GET(MTK_WED_REV_ID_MINOR, wed_ver_id); + recv_id = ((dev_ver << 28) | ver_tmp << 16); + + printk("%s:%d dev_ver=%u recv_id=%u !!!\n",__func__,__LINE__,dev_ver,recv_id); + + if (is_mt7915(&dev->mt76) || dev_ver == MTK_WED_V1) + mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(CAPABILITY), + 0, 0, 0); + else + mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), + MCU_WA_PARAM_WED_VERSION, + recv_id, 0); + mt7915_mcu_set_red(dev, true); +} +else +#endif + mt7915_mcu_set_red(dev, false); ret = mt7915_mcu_set_mwds(dev, 1); if (ret) diff -uNr old/mt7915/mmio.c new/mt7915/mmio.c --- old/mt7915/mmio.c 2023-05-08 12:34:37.269918000 +0800 +++ new/mt7915/mmio.c 2023-05-08 10:56:54.841330000 +0800 @@ -10,6 +10,19 @@ #include "mac.h" #include "../trace.h" #include "../dma.h" +#ifdef CONFIG_SOC_WOE +#include "../mt76_woe.h" +#endif +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD +extern struct sk_buff *(*fromHostadptPktHandle_hook)(unsigned int ringIdx, unsigned char* preschedule); +extern void (*hostdapt_enable_int_hook)(unsigned int ringIdx); +extern void (*hostdapt_disable_int_hook)(unsigned int ringIdx); +extern void (*hostdapt_registe_wifitask_hook)(unsigned int ringIdx, void *func); + +struct mt7915_dev *MT7915_2G; +struct mt7915_dev *MT7915_5G; + +#endif static bool wed_enable = true; module_param(wed_enable, bool, 0644); @@ -724,7 +737,8 @@ int mt7915_mmio_wed_init(struct mt7915_dev *dev, void *pdev_ptr, bool pci, int *irq) { -#ifdef CONFIG_NET_MEDIATEK_SOC_WED +//#ifdef CONFIG_NET_MEDIATEK_SOC_WED +#if 0 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; int ret; @@ -818,7 +832,7 @@ return 1; #else - return 0; + return 1; #endif } @@ -886,32 +900,111 @@ mdev->mmio.irqmask |= set; if (write_reg) { +#if 0 if (mtk_wed_device_active(&mdev->mmio.wed)) mtk_wed_device_irq_set_mask(&mdev->mmio.wed, - mdev->mmio.irqmask); + mdev->mmio.irqmask); + else +#endif +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + mtk_wed_irq_set_mask_woe(mdev, mdev->mmio.irqmask); else mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); +#else + mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask); +#endif mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask); } spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags); } - static void mt7915_rx_poll_complete(struct mt76_dev *mdev, - enum mt76_rxq_id q) + enum mt76_rxq_id q) { struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76); - +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + if(npu_enable()) + { + if(q != MT_RXQ_MAIN && q != MT_RXQ_BAND1)//wifi host not rcv data pkts after enable npu + mt7915_irq_enable(dev, MT_INT_RX(q)); //enable wifi irq + if(dev->dbdc_support) + { + if(q == MT_RXQ_BAND1) + hostdapt_enable_int_hook(1);//enable hostdapt 5G irq + else if(q == MT_RXQ_MAIN) + hostdapt_enable_int_hook(0);//enable hostdapt 2G irq + } + else + { + if(mdev->slot_id) + hostdapt_enable_int_hook(1);//enable hostdapt 5G irq + else + hostdapt_enable_int_hook(0);//enable hostdapt 2G irq + } + } + else + mt7915_irq_enable(dev, MT_INT_RX(q)); +#else mt7915_irq_enable(dev, MT_INT_RX(q)); +#endif } + +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD +int tasklet_schedule_rx_data_done_npu_2G(void) +{ + struct mt7915_dev *dev; + if(MT7915_2G){ + dev=MT7915_2G; + tasklet_schedule(&dev->npu_rx_tasklet_2g); + } + return 0; +} +int tasklet_schedule_rx_data_done_npu_5G(void) +{ + struct mt7915_dev *dev; + if(MT7915_5G){ + dev=MT7915_5G; + tasklet_schedule(&dev->npu_rx_tasklet_5g); + } + return 0; +} +extern int dev_dbdc; +static void mt7915_npu_rx_tasklet(struct tasklet_struct *t) +{ + struct mt7915_dev *dev; + if(MT7915_2G) + { + dev=MT7915_2G; + napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); + } +} + + +static void mt7915_npu_rx_5g_tasklet(struct tasklet_struct *t) +{ + + struct mt7915_dev *dev; + if(MT7915_5G) + { + dev=MT7915_5G; + if(dev_dbdc) + napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1]); + else + napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); + } +} +#endif + + /* TODO: support 2/4/6/8 MSI-X vectors */ static void mt7915_irq_tasklet(struct tasklet_struct *t) { struct mt7915_dev *dev = from_tasklet(dev, t, irq_tasklet); - struct mtk_wed_device *wed = &dev->mt76.mmio.wed; + //struct mtk_wed_device *wed = &dev->mt76.mmio.wed; u32 intr, intr1, mask; - +#if 0 if (mtk_wed_device_active(wed)) { mtk_wed_device_irq_set_mask(wed, 0); if (dev->hif2) @@ -926,6 +1019,26 @@ intr &= dev->mt76.mmio.irqmask; mt76_wr(dev, MT_INT_SOURCE_CSR, intr); } +#endif +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + { + mtk_wed_irq_set_mask(dev, 0); + if (dev->hif2) + mt76_wr(dev, MT_INT1_MASK_CSR, 0); + intr = mtk_wed_irq_get(dev, dev->mt76.mmio.irqmask); + } + else +#endif + { + mt76_wr(dev, MT_INT_MASK_CSR, 0); + if (dev->hif2) + mt76_wr(dev, MT_INT1_MASK_CSR, 0); + + intr = mt76_rr(dev, MT_INT_SOURCE_CSR); + intr &= dev->mt76.mmio.irqmask; + mt76_wr(dev, MT_INT_SOURCE_CSR, intr); + } if (dev->hif2) { intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR); @@ -946,11 +1059,21 @@ if (intr & MT_INT_TX_DONE_MCU) napi_schedule(&dev->mt76.tx_napi); +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + if(!npu_enable()){ + if (intr & MT_INT_RX(MT_RXQ_MAIN)) + napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); + if (intr & MT_INT_RX(MT_RXQ_BAND1)) + napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1]); + } +#else if (intr & MT_INT_RX(MT_RXQ_MAIN)) napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]); - if (intr & MT_INT_RX(MT_RXQ_BAND1)) napi_schedule(&dev->mt76.napi[MT_RXQ_BAND1]); + +#endif + if (intr & MT_INT_RX(MT_RXQ_MCU)) napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]); @@ -979,13 +1102,22 @@ irqreturn_t mt7915_irq_handler(int irq, void *dev_instance) { struct mt7915_dev *dev = dev_instance; +#if 0 struct mtk_wed_device *wed = &dev->mt76.mmio.wed; if (mtk_wed_device_active(wed)) mtk_wed_device_irq_set_mask(wed, 0); else mt76_wr(dev, MT_INT_MASK_CSR, 0); - +#endif +#ifdef CONFIG_SOC_WOE + if(woe_enable()) + mtk_wed_irq_set_mask(dev, 0); + else + mt76_wr(dev, MT_INT_MASK_CSR, 0); +#else + mt76_wr(dev, MT_INT_MASK_CSR, 0); +#endif if (dev->hif2) mt76_wr(dev, MT_INT1_MASK_CSR, 0); @@ -997,8 +1129,23 @@ return IRQ_HANDLED; } +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + +static bool mt7915_band_config_1(struct mt7915_dev *dev) +{ + bool ret = true; + //dev->phy.band_idx = 0; + ret = is_mt7915(&dev->mt76) ? + !!(mt76_rr(dev, MT_HW_BOUND) & BIT(5)) : true; + return ret; +} +struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, + void __iomem *mem_base, u32 device_id,struct pci_dev *pci_dev) +#else struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, void __iomem *mem_base, u32 device_id) +#endif + { static const struct mt76_driver_ops drv_ops = { /* txwi_size = txd size + txp size */ @@ -1023,6 +1170,9 @@ struct mt7915_dev *dev; struct mt76_dev *mdev; int ret; +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + unsigned char band; +#endif mdev = mt76_alloc_device(pdev, sizeof(*dev), &mt7915_ops, &drv_ops); if (!mdev) @@ -1035,6 +1185,62 @@ goto error; tasklet_setup(&dev->irq_tasklet, mt7915_irq_tasklet); +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + if (pci_dev->bus) + band = (pci_dev->bus->self->devfn >> 3) & 0x1f; + else + band = 1; + dev_dbdc = mt7915_band_config_1(dev); + if(npu_enable()){ + if(dev_dbdc) + { + if(hostdapt_registe_wifitask_hook){ + hostdapt_registe_wifitask_hook(0, tasklet_schedule_rx_data_done_npu_2G); + } + + tasklet_setup(&dev->npu_rx_tasklet_2g, mt7915_npu_rx_tasklet); + MT7915_2G=dev; + + if(hostdapt_registe_wifitask_hook){ + hostdapt_registe_wifitask_hook(1, tasklet_schedule_rx_data_done_npu_5G); + } + + tasklet_setup(&dev->npu_rx_tasklet_5g, mt7915_npu_rx_5g_tasklet); + MT7915_5G=dev; + } + else + { + printk("%s:%d band=%d !!!\n",__func__,__LINE__,band); + if(band == 0) + { + if(hostdapt_registe_wifitask_hook){ + + printk("call HOSTDAPT WIFI HOOK 2G \n"); + hostdapt_registe_wifitask_hook(0, tasklet_schedule_rx_data_done_npu_2G); + } + + printk("init 2G tasklet ! \n"); + tasklet_setup(&dev->npu_rx_tasklet_2g, mt7915_npu_rx_tasklet); + MT7915_2G=dev; + + } + else + { + if(hostdapt_registe_wifitask_hook){ + + printk("call HOSTDAPT WIFI HOOK 5G \n"); + hostdapt_registe_wifitask_hook(1, tasklet_schedule_rx_data_done_npu_5G); + } + + printk("init 5G tasklet ! \n"); + tasklet_setup(&dev->npu_rx_tasklet_5g, mt7915_npu_rx_5g_tasklet); + MT7915_5G=dev; + } + + } + + } +#endif return dev; diff -uNr old/mt7915/mt7915.h new/mt7915/mt7915.h --- old/mt7915/mt7915.h 2023-05-08 12:34:37.249911000 +0800 +++ new/mt7915/mt7915.h 2023-05-06 12:58:33.541737000 +0800 @@ -350,7 +350,7 @@ u32 rxfilter; u64 omac_mask; - + u8 band_idx; u16 noise; s16 coverage_class; @@ -517,6 +517,10 @@ #endif struct delayed_work vow_work; struct mt7915_vow_cfg vow_cfg; +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + struct tasklet_struct npu_rx_tasklet_2g; + struct tasklet_struct npu_rx_tasklet_5g; +#endif }; enum { @@ -554,7 +558,8 @@ { return ((!wiphy_ext_feature_isset(wiphy, NL80211_EXT_FEATURE_AIRTIME_FAIRNESS)) || - mtk_wed_device_active(&dev->mt76.mmio.wed)); + woe_enable()); + // mtk_wed_device_active(&dev->mt76.mmio.wed)); } @@ -614,17 +619,25 @@ { } #endif +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD +struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, + void __iomem *mem_base, u32 device_id,struct pci_dev *pci_dev); +#else struct mt7915_dev *mt7915_mmio_probe(struct device *pdev, void __iomem *mem_base, u32 device_id); +#endif + void mt7915_wfsys_reset(struct mt7915_dev *dev); irqreturn_t mt7915_irq_handler(int irq, void *dev_instance); u64 __mt7915_get_tsf(struct ieee80211_hw *hw, struct mt7915_vif *mvif); -u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id); -void mt7915_wed_trigger_ser(struct mtk_wed_device *wed); + +//u32 mt7915_wed_init_buf(void *ptr, dma_addr_t phys, int token_id); +//void mt7915_wed_trigger_ser(struct mtk_wed_device *wed); int mt7915_register_device(struct mt7915_dev *dev); void mt7915_unregister_device(struct mt7915_dev *dev); void mt7915_eeprom_rebonding(struct mt7915_dev *dev); + int mt7915_eeprom_init(struct mt7915_dev *dev); void mt7915_eeprom_parse_hw_cap(struct mt7915_dev *dev, struct mt7915_phy *phy); diff -uNr old/mt7915/mtk_debugfs.c new/mt7915/mtk_debugfs.c --- old/mt7915/mtk_debugfs.c 2023-05-08 12:34:37.191929000 +0800 +++ new/mt7915/mtk_debugfs.c 2023-05-06 13:00:50.510716000 +0800 @@ -6,6 +6,10 @@ #include "eeprom.h" #ifdef MTK_DEBUG +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD +#include "../mt76_npu_offload.h" +#endif + #define LWTBL_IDX2BASE_ID GENMASK(14, 8) #define LWTBL_IDX2BASE_DW GENMASK(7, 2) #define LWTBL_IDX2BASE(_id, _dw) (MT_DBG_WTBL_BASE | \ @@ -857,7 +861,8 @@ dump_dma_tx_ring_info(s, dev, "T16:FWDL", MT_DBG_TX_RING_CTRL(0)); dump_dma_tx_ring_info(s, dev, "T17:Cmd(H2WM)", MT_DBG_TX_RING_CTRL(1)); - if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) { + //if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) { + if (is_mt7916(&dev->mt76) && woe_enable()) { dump_dma_tx_ring_info(s, dev, "T18:TXD0(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(0)); dump_dma_tx_ring_info(s, dev, "T19:TXD1(H2WA)", MT_DBG_WFDMA_WED_TX_CTRL(1)); } else { @@ -868,7 +873,8 @@ dump_dma_tx_ring_info(s, dev, "T20:Cmd(H2WA)", MT_DBG_TX_RING_CTRL(4)); dump_dma_rx_ring_info(s, dev, "R0:Event(WM2H)", MT_DBG_RX_DATA_RING_CTRL(0)); dump_dma_rx_ring_info(s, dev, "R1:Event(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(1)); - if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) + //if (is_mt7916(&dev->mt76) && mtk_wed_device_active(&dev->mt76.mmio.wed)) + if (is_mt7916(&dev->mt76) && woe_enable()) dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_WFDMA_WED_RX_CTRL(1)); else dump_dma_rx_ring_info(s, dev, "R2:TxDone(WA2H)", MT_DBG_RX_EVENT_RING_CTRL(2)); @@ -3207,7 +3213,10 @@ debugfs_create_devm_seqfile(dev->mt76.dev, "fw_version", dir, mt7915_dump_version); - +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + debugfs_create_devm_seqfile(dev->mt76.dev, "npu_count", dir, + mt7915_npu_count); +#endif debugfs_create_devm_seqfile(dev->mt76.dev, "eeprom_mode", dir, mt7915_show_eeprom_mode); debugfs_create_file("sw_aci", 0600, dir, dev, diff -uNr old/mt7915/pci.c new/mt7915/pci.c --- old/mt7915/pci.c 2022-12-10 20:11:05.000000000 +0800 +++ new/mt7915/pci.c 2023-05-08 10:59:59.452304000 +0800 @@ -11,6 +11,9 @@ #include "mt7915.h" #include "mac.h" #include "../trace.h" +#ifdef CONFIG_SOC_WOE +#include "../mt76_woe.h" +#endif static LIST_HEAD(hif_list); static DEFINE_SPINLOCK(hif_lock); @@ -98,7 +101,95 @@ return 0; } - +#ifdef CONFIG_SOC_WOE +#define O_RDONLY 0x0F01 +/*if have /etc/woe_disable disable woe else enable woe(default enable)*/ +int woe_enable_chk(void) +{ + struct file *filp_r = NULL; + char tempStr[64] = {0}; + char filename[64] = "/etc/woe_disable"; + int ret = 0 , error = 0; + mm_segment_t orgfs; + struct kstat stat; + orgfs = get_fs(); + set_fs(KERNEL_DS); + + error = vfs_stat(filename, &stat); + if(error) + printk("%s:%d error!!!\n",__func__,__LINE__); + + filp_r = filp_open(filename, O_RDONLY, 0); + if (IS_ERR(filp_r)) + { + printk("-->2) Error %ld opening %s\n", -PTR_ERR(filp_r), filename); + ret = 1; + goto out1; + } + memset(tempStr, 0x00, sizeof(tempStr)); + ecnt_kernel_fs_read(filp_r, tempStr, sizeof(tempStr), &filp_r->f_pos); + + if(strstr(tempStr,"1")) + printk("%s:%d enable woe !!!\n",__func__,__LINE__); + else + { + printk("%s:%d disable woe !!!\n",__func__,__LINE__); + //ret = 0; /*because always read NULL, so if access file enable woe*/ + } +out: + filp_close(filp_r, NULL); + set_fs(orgfs); + return ret; +out1: + set_fs(orgfs); + return ret; +} +#endif +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD +#define O_RDONLY 0x0F01 +/*if have /etc/woe_disable disable woe else enable woe(default enable)*/ +int npu_enable_chk(void) +{ + struct file *filp_r = NULL; + char tempStr[64] = {0}; + char filename[64] = "/etc/npu_enable"; + int ret = 0 , error = 0; + mm_segment_t orgfs; + struct kstat stat; + orgfs = get_fs(); + set_fs(KERNEL_DS); + + error = vfs_stat(filename, &stat); + if(error) + printk("%s:%d error!!!\n",__func__,__LINE__); + + filp_r = filp_open(filename, O_RDONLY, 0); + if (IS_ERR(filp_r)) + { + printk("npu npu_controller setting \n default open npu %ld opening %s\n", -PTR_ERR(filp_r), filename); + ret = 1; + goto out1; + } + memset(tempStr, 0x00, sizeof(tempStr)); + ecnt_kernel_fs_read(filp_r, tempStr, sizeof(tempStr), &filp_r->f_pos); + + if(strstr(tempStr,"1")){ + printk("%s:%d enable npu !!!\n",__func__,__LINE__); + ret =1 ; + } + else{ + printk("%s:%d disable npu !!!\n",__func__,__LINE__); + //ret = 0; /*because always read NULL, so if access file enable woe*/ + } +out: + filp_close(filp_r, NULL); + set_fs(orgfs); + return ret; +out1: + set_fs(orgfs); + return ret; +} +#endif static int mt7915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { @@ -107,6 +198,12 @@ struct mt76_dev *mdev; int irq; int ret; +#ifdef CONFIG_SOC_WOE + set_woe_enable(woe_enable_chk()); +#endif +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + set_npu_enable(npu_enable_chk()); +#endif ret = pcim_enable_device(pdev); if (ret) @@ -127,8 +224,14 @@ if (id->device == 0x7916 || id->device == 0x790a) return mt7915_pci_hif2_probe(pdev); +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + dev = mt7915_mmio_probe(&pdev->dev, pcim_iomap_table(pdev)[0], + id->device,pdev); +#else dev = mt7915_mmio_probe(&pdev->dev, pcim_iomap_table(pdev)[0], id->device); +#endif + if (IS_ERR(dev)) return PTR_ERR(dev); @@ -139,6 +242,13 @@ ret = mt7915_mmio_wed_init(dev, pdev, true, &irq); if (ret < 0) goto free_wed_or_irq_vector; +#ifdef CONFIG_SOC_WOE + /************************************/ + if(woe_enable()) + woe_start(pdev, mdev, pcim_iomap_table(pdev)[0], pci_resource_start(pdev, 0) + MT_WFDMA_EXT_CSR_BASE); + /************************************/ +#endif + irq = pdev->irq; if (!ret) { hif2 = mt7915_pci_init_hif2(pdev); @@ -178,6 +288,16 @@ ret = mt7915_register_device(dev); if (ret) goto free_hif2_irq; +#ifdef TCSUPPORT_NPU_WIFI_OFFLOAD + if(npu_enable()){ + wifi_offload_init_npu(pdev,dev,0); + npu_init_rxD(dev,pdev); + get_npu_rxd(dev,pdev); + } +#endif + /*modify MT7915A 2G txop config to improve Tx TP*/ + if(is_mt7915(&dev->mt76) && !dev->dbdc_support && dev->phy.band_idx == 0) + mt76_wr(dev, MT_TMAC_TCR2(0), 0Xbb0000); return 0; @@ -189,9 +309,11 @@ put_device(dev->hif2->dev); devm_free_irq(mdev->dev, irq, dev); free_wed_or_irq_vector: +#if 0 if (mtk_wed_device_active(&mdev->mmio.wed)) mtk_wed_device_detach(&mdev->mmio.wed); else +#endif pci_free_irq_vectors(pdev); free_device: mt76_free_device(&dev->mt76); diff -uNr old/mt7915/soc.c new/mt7915/soc.c --- old/mt7915/soc.c 2023-05-08 12:34:35.833907000 +0800 +++ new/mt7915/soc.c 2023-05-08 13:42:12.799629000 +0800 @@ -1218,8 +1218,10 @@ free_irq: devm_free_irq(mdev->dev, irq, dev); free_device: +#if 0 if (mtk_wed_device_active(&mdev->mmio.wed)) mtk_wed_device_detach(&mdev->mmio.wed); +#endif mt76_free_device(mdev); return ret;