/* MUX */ #define EN7523_REG_GPIO_2ND_I2C_MODE 0x0210 #define EN7523_REG_GPIO_SPI_CS1_MODE 0x0214 #define EN7523_REG_GPIO_PON_MODE 0x0218 #define EN7523_REG_NPU_UART_EN 0x0220 #define NPU_UART_MODE_MASK BIT(2) /* CONF */ /* REG_I2C_SDA_PU */ #define EN7523_SPI_MISO_PU_MASK BIT(13) #define EN7523_SPI_MOSI_PU_MASK BIT(12) #define EN7523_SPI_CLK_PU_MASK BIT(11) #define EN7523_SPI_CS0_PU_MASK BIT(10) /* REG_I2C_SDA_PD */ #define EN7523_SPI_MISO_PD_MASK BIT(13) #define EN7523_SPI_MOSI_PD_MASK BIT(12) #define EN7523_SPI_CLK_PD_MASK BIT(11) #define EN7523_SPI_CS0_PD_MASK BIT(10) /* REG_I2C_SDA_E2 */ #define EN7523_SPI_MISO_E2_MASK BIT(13) #define EN7523_SPI_MOSI_E2_MASK BIT(12) #define EN7523_SPI_CLK_E2_MASK BIT(11) #define EN7523_SPI_CS0_E2_MASK BIT(10) /* REG_I2C_SDA_E4 */ #define EN7523_SPI_MISO_E4_MASK BIT(13) #define EN7523_SPI_MOSI_E4_MASK BIT(12) #define EN7523_SPI_CLK_E4_MASK BIT(11) #define EN7523_SPI_CS0_E4_MASK BIT(10) /* LED MAP */ #define EN7523_REG_LAN_LED0_MAPPING 0x0278 #define EN7523_REG_LAN_LED1_MAPPING 0x027c #define EN7523_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ { \ .name = (gpio), \ .regmap[0] = { \ AIROHA_FUNC_MUX, \ EN7523_REG_GPIO_2ND_I2C_MODE, \ (mux_val), \ (mux_val), \ }, \ .regmap[1] = { \ AIROHA_FUNC_MUX, \ EN7523_REG_LAN_LED0_MAPPING, \ (map_mask), \ (map_val), \ }, \ .regmap_size = 2, \ } #define EN7523_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ { \ .name = (gpio), \ .regmap[0] = { \ AIROHA_FUNC_MUX, \ EN7523_REG_GPIO_2ND_I2C_MODE, \ (mux_val), \ (mux_val), \ }, \ .regmap[1] = { \ AIROHA_FUNC_MUX, \ EN7523_REG_LAN_LED1_MAPPING, \ (map_mask), \ (map_val), \ }, \ .regmap_size = 2, \ } static struct pinctrl_pin_desc en7523_pins[] = { PINCTRL_PIN(1, "hw_rstn"), PINCTRL_PIN(2, "i2c_sda"), PINCTRL_PIN(3, "i2c_scl"), PINCTRL_PIN(4, "spi_cs0"), PINCTRL_PIN(5, "spi_clk"), PINCTRL_PIN(6, "spi_mosi"), PINCTRL_PIN(7, "spi_miso"), PINCTRL_PIN(8, "uart1_txd"), PINCTRL_PIN(9, "uart1_rxd"), PINCTRL_PIN(10, "efuse"), PINCTRL_PIN(11, "pkg_sel"), PINCTRL_PIN(12, "gpio0"), PINCTRL_PIN(13, "gpio1"), PINCTRL_PIN(14, "gpio2"), PINCTRL_PIN(15, "gpio3"), PINCTRL_PIN(16, "gpio4"), PINCTRL_PIN(17, "gpio5"), PINCTRL_PIN(18, "gpio6"), PINCTRL_PIN(19, "gpio7"), PINCTRL_PIN(20, "gpio8"), PINCTRL_PIN(21, "gpio9"), PINCTRL_PIN(22, "gpio10"), PINCTRL_PIN(23, "gpio11"), PINCTRL_PIN(24, "gpio12"), PINCTRL_PIN(25, "gpio13"), PINCTRL_PIN(26, "gpio14"), PINCTRL_PIN(27, "gpio15"), PINCTRL_PIN(28, "gpio16"), PINCTRL_PIN(29, "gpio17"), PINCTRL_PIN(30, "gpio18"), PINCTRL_PIN(31, "gpio19"), PINCTRL_PIN(32, "gpio20"), PINCTRL_PIN(33, "gpio21"), PINCTRL_PIN(34, "gpio22"), PINCTRL_PIN(35, "gpio23"), PINCTRL_PIN(36, "gpio24"), PINCTRL_PIN(37, "gpio25"), PINCTRL_PIN(38, "gpio26"), PINCTRL_PIN(39, "gpio27"), PINCTRL_PIN(40, "pcie_reset0"), PINCTRL_PIN(41, "pcie_reset1"), }; static const int en7523_pon_pins[] = { 28, 29, 30, 32, 33 }; static const int en7523_tod_pins[] = { 21 }; static const int en7523_sipo_pins[] = { 13, 38 }; static const int en7523_sipo_rclk_pins[] = { 13, 30, 38 }; static const int en7523_mdio_pins[] = { 20, 21 }; static const int en7523_uart2_pins[] = { 20, 21 }; static const int en7523_i2c1_pins[] = { 8, 9 }; static const int en7523_jtag_udi_pins[] = { 34, 35, 36, 37, 38 }; static const int en7523_jtag_dfd_pins[] = { 34, 35, 36, 37, 38 }; static const int en7523_i2s0_pins[] = { 16, 17, 18, 19 }; static const int en7523_pcm1_pins[] = { 24, 25, 26, 27 }; static const int en7523_pcm2_pins[] = { 16, 17, 18, 19 }; static const int en7523_spi_quad_pins[] = { 14, 15 }; static const int en7523_spi_cs1_pins[] = { 21 }; static const int en7523_pcm_spi_pins[] = { 16, 17, 18, 19, 24, 25, 26, 27 }; static const int en7523_pcm_spi_int_pins[] = { 15 }; static const int en7523_pcm_spi_rst_pins[] = { 14 }; static const int en7523_pcm_spi_cs1_pins[] = { 22 }; static const int en7523_pcm_spi_cs2_p128_pins[] = { 41 }; static const int en7523_pcm_spi_cs2_p156_pins[] = { 39 }; static const int en7523_pcm_spi_cs3_pins[] = { 20 }; static const int en7523_pcm_spi_cs4_pins[] = { 23 }; static const int en7523_npu_uart_pins[] = { 13, 38 }; static const int en7523_gpio0_pins[] = { 12 }; static const int en7523_gpio1_pins[] = { 13 }; static const int en7523_gpio2_pins[] = { 14 }; static const int en7523_gpio3_pins[] = { 15 }; static const int en7523_gpio4_pins[] = { 16 }; static const int en7523_gpio5_pins[] = { 17 }; static const int en7523_gpio6_pins[] = { 18 }; static const int en7523_gpio7_pins[] = { 19 }; static const int en7523_gpio8_pins[] = { 20 }; static const int en7523_gpio9_pins[] = { 21 }; static const int en7523_gpio10_pins[] = { 22 }; static const int en7523_gpio11_pins[] = { 23 }; static const int en7523_gpio12_pins[] = { 24 }; static const int en7523_gpio13_pins[] = { 25 }; static const int en7523_gpio14_pins[] = { 26 }; static const int en7523_gpio15_pins[] = { 27 }; static const int en7523_gpio16_pins[] = { 28 }; static const int en7523_gpio17_pins[] = { 29 }; static const int en7523_gpio18_pins[] = { 30 }; static const int en7523_gpio19_pins[] = { 31 }; static const int en7523_gpio20_pins[] = { 32 }; static const int en7523_gpio21_pins[] = { 33 }; static const int en7523_gpio22_pins[] = { 34 }; static const int en7523_gpio23_pins[] = { 35 }; static const int en7523_gpio24_pins[] = { 36 }; static const int en7523_gpio25_pins[] = { 37 }; static const int en7523_gpio26_pins[] = { 38 }; static const int en7523_gpio27_pins[] = { 39 }; static const int en7523_gpio28_pins[] = { 40 }; static const int en7523_gpio29_pins[] = { 41 }; static const int en7523_pcie_reset0_pins[] = { 40 }; static const int en7523_pcie_reset1_pins[] = { 41 }; static const struct pingroup en7523_pinctrl_groups[] = { PINCTRL_PIN_GROUP("pon", en7523_pon), PINCTRL_PIN_GROUP("pon_tod_1pps", en7523_tod), PINCTRL_PIN_GROUP("gsw_tod_1pps", en7523_tod), PINCTRL_PIN_GROUP("sipo", en7523_sipo), PINCTRL_PIN_GROUP("sipo_rclk", en7523_sipo_rclk), PINCTRL_PIN_GROUP("mdio", en7523_mdio), PINCTRL_PIN_GROUP("uart2", en7523_uart2), PINCTRL_PIN_GROUP("i2c1", en7523_i2c1), PINCTRL_PIN_GROUP("jtag_udi", en7523_jtag_udi), PINCTRL_PIN_GROUP("jtag_dfd", en7523_jtag_dfd), PINCTRL_PIN_GROUP("i2s", en7523_i2s), PINCTRL_PIN_GROUP("pcm1", en7523_pcm1), PINCTRL_PIN_GROUP("pcm2", en7523_pcm2), PINCTRL_PIN_GROUP("spi_quad", en7523_spi_quad), PINCTRL_PIN_GROUP("spi_cs1", en7523_spi_cs1), PINCTRL_PIN_GROUP("pcm_spi", en7523_pcm_spi), PINCTRL_PIN_GROUP("pcm_spi_int", en7523_pcm_spi_int), PINCTRL_PIN_GROUP("pcm_spi_rst", en7523_pcm_spi_rst), PINCTRL_PIN_GROUP("pcm_spi_cs1", en7523_pcm_spi_cs1), PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7523_pcm_spi_cs2_p128), PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7523_pcm_spi_cs2_p156), PINCTRL_PIN_GROUP("pcm_spi_cs2", en7523_pcm_spi_cs2), PINCTRL_PIN_GROUP("pcm_spi_cs3", en7523_pcm_spi_cs3), PINCTRL_PIN_GROUP("pcm_spi_cs4", en7523_pcm_spi_cs4), PINCTRL_PIN_GROUP("npu_uart", npu_uart), PINCTRL_PIN_GROUP("gpio0", en7523_gpio0), PINCTRL_PIN_GROUP("gpio1", en7523_gpio1), PINCTRL_PIN_GROUP("gpio2", en7523_gpio2), PINCTRL_PIN_GROUP("gpio3", en7523_gpio3), PINCTRL_PIN_GROUP("gpio4", en7523_gpio4), PINCTRL_PIN_GROUP("gpio5", en7523_gpio5), PINCTRL_PIN_GROUP("gpio6", en7523_gpio6), PINCTRL_PIN_GROUP("gpio7", en7523_gpio7), PINCTRL_PIN_GROUP("gpio8", en7523_gpio8), PINCTRL_PIN_GROUP("gpio9", en7523_gpio9), PINCTRL_PIN_GROUP("gpio10", en7523_gpio10), PINCTRL_PIN_GROUP("gpio11", en7523_gpio11), PINCTRL_PIN_GROUP("gpio12", en7523_gpio12), PINCTRL_PIN_GROUP("gpio13", en7523_gpio13), PINCTRL_PIN_GROUP("gpio14", en7523_gpio14), PINCTRL_PIN_GROUP("gpio15", en7523_gpio15), PINCTRL_PIN_GROUP("gpio16", en7523_gpio16), PINCTRL_PIN_GROUP("gpio17", en7523_gpio17), PINCTRL_PIN_GROUP("gpio18", en7523_gpio18), PINCTRL_PIN_GROUP("gpio19", en7523_gpio19), PINCTRL_PIN_GROUP("gpio20", en7523_gpio20), PINCTRL_PIN_GROUP("gpio21", en7523_gpio21), PINCTRL_PIN_GROUP("gpio22", en7523_gpio22), PINCTRL_PIN_GROUP("gpio23", en7523_gpio23), PINCTRL_PIN_GROUP("gpio24", en7523_gpio24), PINCTRL_PIN_GROUP("gpio25", en7523_gpio25), PINCTRL_PIN_GROUP("gpio26", en7523_gpio26), PINCTRL_PIN_GROUP("gpio27", en7523_gpio27), PINCTRL_PIN_GROUP("gpio28", en7523_gpio28), PINCTRL_PIN_GROUP("gpio29", en7523_gpio29), PINCTRL_PIN_GROUP("pcie_reset0", en7523_pcie_reset0), PINCTRL_PIN_GROUP("pcie_reset1", en7523_pcie_reset1), }; static const char *const en7523_uart_groups[] = { "uart2", "npu_uart" }; static const char *const en7523_pwm_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", }; static const char *const en7523_phy1_led0_groups[] = { "gpio4", "gpio5", "gpio6", "gpio7" }; static const char *const en7523_phy2_led0_groups[] = { "gpio4", "gpio5", "gpio6", "gpio7" }; static const char *const en7523_phy3_led0_groups[] = { "gpio4", "gpio5", "gpio6", "gpio7" }; static const char *const en7523_phy4_led0_groups[] = { "gpio4", "gpio5", "gpio6", "gpio7" }; static const char *const en7523_phy1_led1_groups[] = { "gpio22", "gpio23", "gpio24", "gpio25" }; static const char *const en7523_phy2_led1_groups[] = { "gpio22", "gpio23", "gpio24", "gpio25" }; static const char *const en7523_phy3_led1_groups[] = { "gpio22", "gpio23", "gpio24", "gpio25" }; static const char *const en7523_phy4_led1_groups[] = { "gpio22", "gpio23", "gpio24", "gpio25" }; static const struct airoha_pinctrl_func_group pon_func_group[] = { { .name = "pon", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, GPIO_PON_MODE_MASK, GPIO_PON_MODE_MASK }, .regmap_size = 1, }, }; static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { { .name = "pon_tod_1pps", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_2ND_I2C_MODE, PON_TOD_1PPS_MODE_MASK, PON_TOD_1PPS_MODE_MASK }, .regmap_size = 1, }, { .name = "gsw_tod_1pps", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_2ND_I2C_MODE, GSW_TOD_1PPS_MODE_MASK, GSW_TOD_1PPS_MODE_MASK }, .regmap_size = 1, }, }; static const struct airoha_pinctrl_func_group sipo_func_group[] = { { .name = "sipo", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, GPIO_SIPO_MODE_MASK }, .regmap_size = 1, }, { .name = "sipo_rclk", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK }, .regmap_size = 1, }, }; static const struct airoha_pinctrl_func_group mdio_func_group[] = { { .name = "mdio", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_2ND_I2C_MODE, GPIO_MDC_IO_MASTER_MODE_MODE, GPIO_MDC_IO_MASTER_MODE_MODE }, .regmap_size = 1, }, }; static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = { { .name = "mdio", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, GPIO_SGMII_MDIO_MODE_MASK, GPIO_SGMII_MDIO_MODE_MASK }, .regmap_size = 1, }, }; static const struct airoha_pinctrl_func_group uart_func_group[] = { { .name = "uart2", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, GPIO_UART2_MODE_MASK, GPIO_UART2_MODE_MASK }, .regmap_size = 1, }, }; static const struct airoha_pinctrl_func_group jtag_func_group[] = { { .name = "jtag_udi", .regmap[0] = { AIROHA_FUNC_MUX, REG_NPU_UART_EN, JTAG_UDI_EN_MASK, JTAG_UDI_EN_MASK }, .regmap_size = 1, }, { .name = "jtag_dfd", .regmap[0] = { AIROHA_FUNC_MUX, REG_NPU_UART_EN, JTAG_DFD_EN_MASK, JTAG_DFD_EN_MASK }, .regmap_size = 1, }, }; static const struct airoha_pinctrl_func_group pcm_func_group[] = { { .name = "pcm1", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_PCM1_MODE_MASK, GPIO_PCM1_MODE_MASK }, .regmap_size = 1, }, { .name = "pcm2", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_PCM2_MODE_MASK, GPIO_PCM2_MODE_MASK }, .regmap_size = 1, }, }; static const struct airoha_pinctrl_func_group spi_func_group[] = { { .name = "spi_quad", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_SPI_QUAD_MODE_MASK, GPIO_SPI_QUAD_MODE_MASK }, .regmap_size = 1, }, { .name = "spi_cs1", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_SPI_CS1_MODE_MASK, GPIO_SPI_CS1_MODE_MASK }, .regmap_size = 1, }, { .name = "spi_cs2", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_SPI_CS2_MODE_MASK, GPIO_SPI_CS2_MODE_MASK }, .regmap_size = 1, }, { .name = "spi_cs3", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_SPI_CS3_MODE_MASK, GPIO_SPI_CS3_MODE_MASK }, .regmap_size = 1, }, { .name = "spi_cs4", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_SPI_CS4_MODE_MASK, GPIO_SPI_CS4_MODE_MASK }, .regmap_size = 1, }, }; static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { { .name = "pcm_spi", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_MODE_MASK, GPIO_PCM_SPI_MODE_MASK }, .regmap_size = 1, }, { .name = "pcm_spi_int", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_PCM_INT_MODE_MASK, GPIO_PCM_INT_MODE_MASK }, .regmap_size = 1, }, { .name = "pcm_spi_rst", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_PCM_RESET_MODE_MASK, GPIO_PCM_RESET_MODE_MASK }, .regmap_size = 1, }, { .name = "pcm_spi_cs1", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_CS1_MODE_MASK, GPIO_PCM_SPI_CS1_MODE_MASK }, .regmap_size = 1, }, { .name = "pcm_spi_cs2_p128", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_CS2_MODE_P128_MASK, GPIO_PCM_SPI_CS2_MODE_P128_MASK }, .regmap_size = 1, }, { .name = "pcm_spi_cs2_p156", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_CS2_MODE_P156_MASK, GPIO_PCM_SPI_CS2_MODE_P156_MASK }, .regmap_size = 1, }, { .name = "pcm_spi_cs3", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_CS3_MODE_MASK, GPIO_PCM_SPI_CS3_MODE_MASK }, .regmap_size = 1, }, { .name = "pcm_spi_cs4", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_SPI_CS1_MODE, GPIO_PCM_SPI_CS4_MODE_MASK, GPIO_PCM_SPI_CS4_MODE_MASK }, .regmap_size = 1, }, }; static const struct airoha_pinctrl_func_group i2s_func_group[] = { { .name = "i2s", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_2ND_I2C_MODE, GPIO_I2S_MODE_MASK, GPIO_I2S_MODE_MASK }, .regmap_size = 1, }, }; static const struct airoha_pinctrl_func_group e7523_pcie_reset_func_group[] = { { .name = "pcie_reset0", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, GPIO_PCIE_RESET0_MASK, GPIO_PCIE_RESET0_MASK }, .regmap_size = 1, }, { .name = "pcie_reset1", .regmap[0] = { AIROHA_FUNC_MUX, REG_GPIO_PON_MODE, GPIO_PCIE_RESET1_MASK, GPIO_PCIE_RESET1_MASK }, .regmap_size = 1, }, }; static const struct airoha_pinctrl_func_group en7523_phy1_led0_func_group[] = { EN7523_PINCTRL_PHY_LED0("gpio4", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), EN7523_PINCTRL_PHY_LED0("gpio5", GPIO_LAN1_LED0_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), EN7523_PINCTRL_PHY_LED0("gpio6", GPIO_LAN2_LED0_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), EN7523_PINCTRL_PHY_LED0("gpio7", GPIO_LAN3_LED0_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), }; static const struct airoha_pinctrl_func_group en7523_phy2_led0_func_group[] = { EN7523_PINCTRL_PHY_LED0("gpio4", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), EN7523_PINCTRL_PHY_LED0("gpio5", GPIO_LAN1_LED0_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), EN7523_PINCTRL_PHY_LED0("gpio6", GPIO_LAN2_LED0_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), EN7523_PINCTRL_PHY_LED0("gpio7", GPIO_LAN3_LED0_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), }; static const struct airoha_pinctrl_func_group en7523_phy3_led0_func_group[] = { EN7523_PINCTRL_PHY_LED0("gpio4", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), EN7523_PINCTRL_PHY_LED0("gpio5", GPIO_LAN1_LED0_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), EN7523_PINCTRL_PHY_LED0("gpio6", GPIO_LAN2_LED0_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), EN7523_PINCTRL_PHY_LED0("gpio7", GPIO_LAN3_LED0_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; static const struct airoha_pinctrl_func_group en7523_phy4_led0_func_group[] = { EN7523_PINCTRL_PHY_LED0("gpio4", GPIO_LAN0_LED0_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), EN7523_PINCTRL_PHY_LED0("gpio5", GPIO_LAN1_LED0_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), EN7523_PINCTRL_PHY_LED0("gpio6", GPIO_LAN2_LED0_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), EN7523_PINCTRL_PHY_LED0("gpio7", GPIO_LAN3_LED0_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), }; static const struct airoha_pinctrl_func_group en7523_phy1_led1_func_group[] = { EN7523_PINCTRL_PHY_LED1("gpio22", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), EN7523_PINCTRL_PHY_LED1("gpio23", GPIO_LAN1_LED1_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), EN7523_PINCTRL_PHY_LED1("gpio24", GPIO_LAN2_LED1_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), EN7523_PINCTRL_PHY_LED1("gpio25", GPIO_LAN3_LED1_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), }; static const struct airoha_pinctrl_func_group en7523_phy2_led1_func_group[] = { EN7523_PINCTRL_PHY_LED1("gpio22", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), EN7523_PINCTRL_PHY_LED1("gpio23", GPIO_LAN1_LED1_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), EN7523_PINCTRL_PHY_LED1("gpio24", GPIO_LAN2_LED1_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), EN7523_PINCTRL_PHY_LED1("gpio25", GPIO_LAN3_LED1_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), }; static const struct airoha_pinctrl_func_group en7523_phy3_led1_func_group[] = { EN7523_PINCTRL_PHY_LED1("gpio22", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), EN7523_PINCTRL_PHY_LED1("gpio23", GPIO_LAN1_LED1_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), EN7523_PINCTRL_PHY_LED1("gpio24", GPIO_LAN2_LED1_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), EN7523_PINCTRL_PHY_LED1("gpio25", GPIO_LAN3_LED1_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; static const struct airoha_pinctrl_func_group en7523_phy4_led1_func_group[] = { EN7523_PINCTRL_PHY_LED1("gpio22", GPIO_LAN0_LED1_MODE_MASK, LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), EN7523_PINCTRL_PHY_LED1("gpio23", GPIO_LAN1_LED1_MODE_MASK, LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), EN7523_PINCTRL_PHY_LED1("gpio24", GPIO_LAN2_LED1_MODE_MASK, LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), EN7523_PINCTRL_PHY_LED1("gpio25", GPIO_LAN3_LED1_MODE_MASK, LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), }; static const struct airoha_pinctrl_func en7523_pinctrl_funcs[] = { PINCTRL_FUNC_DESC("pon", pon), PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), PINCTRL_FUNC_DESC("sipo", sipo), PINCTRL_FUNC_DESC("mdio", mdio), PINCTRL_FUNC_DESC("uart", en7523_uart), PINCTRL_FUNC_DESC("jtag", jtag), PINCTRL_FUNC_DESC("pcm", pcm), PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), PINCTRL_FUNC_DESC("i2s", i2s), PINCTRL_FUNC_DESC("pcie_reset", en7523_pcie_reset), PINCTRL_FUNC_DESC("pwm", en7523_pwm), PINCTRL_FUNC_DESC("phy1_led0", en7523_phy1_led0), PINCTRL_FUNC_DESC("phy2_led0", en7523_phy2_led0), PINCTRL_FUNC_DESC("phy3_led0", en7523_phy3_led0), PINCTRL_FUNC_DESC("phy4_led0", en7523_phy4_led0), PINCTRL_FUNC_DESC("phy1_led1", en7523_phy1_led1), PINCTRL_FUNC_DESC("phy2_led1", en7523_phy2_led1), PINCTRL_FUNC_DESC("phy3_led1", en7523_phy3_led1), PINCTRL_FUNC_DESC("phy4_led1", en7523_phy4_led1), }; static const struct airoha_pinctrl_conf en7523_pinctrl_pullup_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, EN7523_SPI_CS0_PU_MASK), PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, EN7523_SPI_CLK_PU_MASK), PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, EN7523_SPI_MOSI_PU_MASK), PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, EN7523_SPI_MISO_PU_MASK), PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(0)), PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(1)), PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(2)), PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(3)), PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(4)), PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(5)), PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(6)), PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(7)), PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(8)), PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(9)), PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(10)), PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(11)), PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(12)), PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(13)), PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(14)), PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(15)), PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(16)), PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(17)), PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(18)), PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(20)), PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(21)), PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(22)), PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(23)), PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(24)), PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(25)), PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(26)), PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(27)), PINCTRL_CONF_DESC(40, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), }; static const struct airoha_pinctrl_conf en7523_pinctrl_pulldown_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, EN7523_SPI_CS0_PD_MASK), PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, EN7523_SPI_CLK_PD_MASK), PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, EN7523_SPI_MOSI_PD_MASK), PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, EN7523_SPI_MISO_PD_MASK), PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(0)), PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(1)), PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(2)), PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(3)), PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(4)), PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(5)), PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(6)), PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(7)), PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(8)), PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(9)), PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(10)), PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(11)), PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(12)), PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(13)), PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(14)), PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(15)), PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(16)), PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(17)), PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(18)), PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(20)), PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(21)), PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(22)), PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(23)), PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(24)), PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(25)), PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(26)), PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(27)), PINCTRL_CONF_DESC(40, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), }; static const struct airoha_pinctrl_conf en7523_pinctrl_drive_e2_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, EN7523_SPI_CS0_E2_MASK), PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, EN7523_SPI_CLK_E2_MASK), PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, EN7523_SPI_MOSI_E2_MASK), PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, EN7523_SPI_MISO_E2_MASK), PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(0)), PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(1)), PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(2)), PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(3)), PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(4)), PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(5)), PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(6)), PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(7)), PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(8)), PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(9)), PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(10)), PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(11)), PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(12)), PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(13)), PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(14)), PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(15)), PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(16)), PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(17)), PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(18)), PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(20)), PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(21)), PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(22)), PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(23)), PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(24)), PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(25)), PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(26)), PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(27)), PINCTRL_CONF_DESC(40, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), }; static const struct airoha_pinctrl_conf en7523_pinctrl_drive_e4_conf[] = { PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, EN7523_SPI_CS0_E4_MASK), PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, EN7523_SPI_CLK_E4_MASK), PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, EN7523_SPI_MOSI_E4_MASK), PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, EN7523_SPI_MISO_E4_MASK), PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(0)), PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(1)), PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(2)), PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(3)), PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(4)), PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(5)), PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(6)), PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(7)), PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(8)), PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(9)), PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(10)), PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(11)), PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(12)), PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(13)), PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(14)), PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(15)), PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(16)), PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(17)), PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(18)), PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(20)), PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(21)), PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(22)), PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(23)), PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(24)), PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(25)), PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(26)), PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(27)), PINCTRL_CONF_DESC(40, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), }; static const struct airoha_pinctrl_conf en7523_pinctrl_pcie_rst_od_conf[] = { PINCTRL_CONF_DESC(40, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), PINCTRL_CONF_DESC(41, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), };