mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2026-07-02 05:42:41 +00:00
Masahiro Yamada
a7739bc7b1
Move the bss section to the common header. This adds BAKERY_LOCK_NORMAL and PMF_TIMESTAMP, which previously existed only in BL31. This is not a big deal because unused data should not be compiled in the first place. I believe this should be controlled by BL*_SOURCES in Makefiles, not by linker scripts. I investigated BL1, BL2, BL2U, BL31 for plat=fvp, and BL2-AT-EL3, BL31, BL31 for plat=uniphier. I did not see any more unexpected code addition. The bss section has bigger alignment. I added BSS_ALIGN for this. Currently, SORT_BY_ALIGNMENT() is missing in sp_min.ld.S, and with this change, the BSS symbols in SP_MIN will be sorted by the alignment. This is not a big deal (or, even better in terms of the image size). Change-Id: I680ee61f84067a559bac0757f9d03e73119beb33 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
134 lines
3.4 KiB
ArmAsm
134 lines
3.4 KiB
ArmAsm
/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <platform_def.h>
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#include <common/bl_common.ld.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
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OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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ENTRY(bl2u_entrypoint)
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MEMORY {
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RAM (rwx): ORIGIN = BL2U_BASE, LENGTH = BL2U_LIMIT - BL2U_BASE
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}
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SECTIONS
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{
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. = BL2U_BASE;
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ASSERT(. == ALIGN(PAGE_SIZE),
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"BL2U_BASE address is not aligned on a page boundary.")
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#if SEPARATE_CODE_AND_RODATA
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.text . : {
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__TEXT_START__ = .;
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*bl2u_entrypoint.o(.text*)
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*(SORT_BY_ALIGNMENT(.text*))
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*(.vectors)
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. = ALIGN(PAGE_SIZE);
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__TEXT_END__ = .;
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} >RAM
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/* .ARM.extab and .ARM.exidx are only added because Clang need them */
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.ARM.extab . : {
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} >RAM
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.ARM.exidx . : {
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} >RAM
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.rodata . : {
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__RODATA_START__ = .;
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*(SORT_BY_ALIGNMENT(.rodata*))
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RODATA_COMMON
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. = ALIGN(PAGE_SIZE);
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__RODATA_END__ = .;
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} >RAM
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#else
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ro . : {
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__RO_START__ = .;
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*bl2u_entrypoint.o(.text*)
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*(SORT_BY_ALIGNMENT(.text*))
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*(SORT_BY_ALIGNMENT(.rodata*))
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RODATA_COMMON
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*(.vectors)
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__RO_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked as
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* read-only, executable. No RW data from the next section must
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* creep in. Ensure the rest of the current memory page is unused.
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*/
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. = ALIGN(PAGE_SIZE);
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__RO_END__ = .;
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} >RAM
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#endif
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/*
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* Define a linker symbol to mark start of the RW memory area for this
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* image.
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*/
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__RW_START__ = . ;
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/*
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* .data must be placed at a lower address than the stacks if the stack
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* protector is enabled. Alternatively, the .data.stack_protector_canary
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* section can be placed independently of the main .data section.
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*/
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.data . : {
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__DATA_START__ = .;
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*(SORT_BY_ALIGNMENT(.data*))
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__DATA_END__ = .;
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} >RAM
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stacks (NOLOAD) : {
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__STACKS_START__ = .;
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*(tzfw_normal_stacks)
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__STACKS_END__ = .;
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} >RAM
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BSS_SECTION >RAM
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XLAT_TABLE_SECTION >RAM
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#if USE_COHERENT_MEM
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/*
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* The base address of the coherent memory section must be page-aligned (4K)
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* to guarantee that the coherent data are stored on their own pages and
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* are not mixed with normal data. This is required to set up the correct
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* memory attributes for the coherent data page tables.
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*/
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coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
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__COHERENT_RAM_START__ = .;
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*(tzfw_coherent_mem)
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__COHERENT_RAM_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked
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* as device memory. No other unexpected data must creep in.
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* Ensure the rest of the current memory page is unused.
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*/
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. = ALIGN(PAGE_SIZE);
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__COHERENT_RAM_END__ = .;
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} >RAM
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#endif
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/*
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* Define a linker symbol to mark end of the RW memory area for this
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* image.
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*/
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__RW_END__ = .;
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__BL2U_END__ = .;
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__BSS_SIZE__ = SIZEOF(.bss);
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ASSERT(. <= BL2U_LIMIT, "BL2U image has exceeded its limit.")
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}
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