mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2026-07-02 20:52:40 +00:00
Nicolas Le BayonandYann Gautier
bf4f90bf52
Add STM32MP231 STM32MP233 and STM32MP235 SoC DT files and the 23xC and 23xF overlays for security features. Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Change-Id: Ia813bf957b1f93e4096624f1fe954e3f3cd1575a
619 lines
14 KiB
Devicetree
619 lines
14 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/*
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* Copyright (C) 2026, STMicroelectronics - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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#include <dt-bindings/clock/stm32mp25-clks.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/stm32mp25-resets.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a35";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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domain-idle-states {
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domain-stop1 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x00000011>;
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};
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domain-lp-stop1 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x00000021>;
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};
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domain-lplv-stop1 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x00000211>;
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};
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domain-stop2 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x40001333>;
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};
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domain-lp-stop2 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x40002333>;
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};
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domain-lplv-stop2 {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x40023333>;
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};
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domain-standby {
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compatible = "domain-idle-state";
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arm,psci-suspend-param = <0x40033333>;
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};
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};
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <64000000>;
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_msi: clk-msi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <16000000>;
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};
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};
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intc: interrupt-controller@4ac00000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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interrupt-controller;
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reg = <0x0 0x4ac10000 0x0 0x1000>,
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<0x0 0x4ac20000 0x0 0x2000>,
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<0x0 0x4ac40000 0x0 0x2000>,
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<0x0 0x4ac60000 0x0 0x2000>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&intc>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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always-on;
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};
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soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&intc>;
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ranges = <0x0 0x0 0x0 0x80000000>;
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ommanager: ommanager@40500000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "st,stm32mp25-omm";
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reg = <0x40500000 0x400>, <0x60000000 0x10000000>;
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reg-names = "omm", "omm_mm";
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clocks = <&rcc CK_BUS_OSPIIOM>;
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resets = <&rcc OSPIIOM_R>;
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status = "disabled";
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ranges = <0 0 0x40430000 0x400>,
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<1 0 0x40440000 0x400>;
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ospi1: spi@40430000 {
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compatible = "st,stm32mp25-omi";
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reg = <0 0 0x400>;
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clocks = <&rcc CK_KER_OSPI1>;
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resets = <&rcc OSPI1_R>, <&rcc OSPI1DLL_R>;
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status = "disabled";
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};
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ospi2: spi@40440000 {
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compatible = "st,stm32mp25-omi";
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reg = <1 0 0x400>;
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clocks = <&rcc CK_KER_OSPI2>;
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resets = <&rcc OSPI2_R>, <&rcc OSPI2DLL_R>;
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status = "disabled";
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};
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};
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rifsc: rifsc@42080000 {
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compatible = "st,stm32mp25-rifsc", "syscon";
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reg = <0x42080000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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usart2: serial@400e0000 {
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compatible = "st,stm32h7-uart";
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reg = <0x400e0000 0x400>;
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clocks = <&rcc CK_KER_USART2>;
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resets = <&rcc USART2_R>;
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status = "disabled";
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};
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usart3: serial@400f0000 {
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compatible = "st,stm32h7-uart";
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reg = <0x400f0000 0x400>;
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clocks = <&rcc CK_KER_USART3>;
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resets = <&rcc USART3_R>;
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status = "disabled";
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};
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uart4: serial@40100000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40100000 0x400>;
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clocks = <&rcc CK_KER_UART4>;
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resets = <&rcc UART4_R>;
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status = "disabled";
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};
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uart5: serial@40110000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40110000 0x400>;
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clocks = <&rcc CK_KER_UART5>;
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resets = <&rcc UART5_R>;
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status = "disabled";
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};
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i2c1: i2c@40120000 {
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compatible = "st,stm32mp25-i2c";
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reg = <0x40120000 0x400>;
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clocks = <&rcc CK_KER_I2C1>;
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resets = <&rcc I2C1_R>;
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status = "disabled";
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};
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i2c2: i2c@40130000 {
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compatible = "st,stm32mp25-i2c";
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reg = <0x40130000 0x400>;
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clocks = <&rcc CK_KER_I2C2>;
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resets = <&rcc I2C2_R>;
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status = "disabled";
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};
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i2c7: i2c@40180000 {
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compatible = "st,stm32mp25-i2c";
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reg = <0x40180000 0x400>;
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clocks = <&rcc CK_KER_I2C7>;
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resets = <&rcc I2C7_R>;
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status = "disabled";
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};
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usart6: serial@40220000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40220000 0x400>;
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clocks = <&rcc CK_KER_USART6>;
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resets = <&rcc USART6_R>;
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status = "disabled";
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};
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usart1: serial@40330000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40330000 0x400>;
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clocks = <&rcc CK_KER_USART1>;
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resets = <&rcc USART1_R>;
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status = "disabled";
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};
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uart7: serial@40370000 {
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compatible = "st,stm32h7-uart";
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reg = <0x40370000 0x400>;
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clocks = <&rcc CK_KER_UART7>;
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resets = <&rcc UART7_R>;
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status = "disabled";
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};
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hash: hash@42010000 {
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compatible = "st,stm32mp13-hash";
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reg = <0x42010000 0x400>;
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clocks = <&rcc CK_BUS_HASH>;
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resets = <&rcc HASH_R>;
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status = "disabled";
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};
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rng: rng@42020000 {
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compatible = "st,stm32mp13-rng";
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reg = <0x42020000 0x400>;
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clocks = <&rcc CK_BUS_RNG>;
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resets = <&rcc RNG_R>;
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status = "disabled";
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};
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iwdg1: watchdog@44010000 {
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compatible = "st,stm32mp1-iwdg";
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reg = <0x44010000 0x400>;
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clocks = <&rcc CK_BUS_IWDG1>, <&rcc LSI_CK>;
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clock-names = "pclk", "lsi";
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status = "disabled";
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};
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i2c8: i2c@46040000 {
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compatible = "st,stm32mp25-i2c";
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reg = <0x46040000 0x400>;
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clocks = <&rcc CK_KER_I2C8>;
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resets = <&rcc I2C8_R>;
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status = "disabled";
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};
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sdmmc1: mmc@48220000 {
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compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00353180>;
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reg = <0x48220000 0x400>, <0x44230400 0x8>;
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clocks = <&rcc CK_KER_SDMMC1>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC1_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <166000000>;
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status = "disabled";
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};
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sdmmc2: mmc@48230000 {
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compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
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arm,primecell-periphid = <0x00353180>;
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reg = <0x48230000 0x400>, <0x44230800 0x8>;
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clocks = <&rcc CK_KER_SDMMC2>;
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clock-names = "apb_pclk";
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resets = <&rcc SDMMC2_R>;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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max-frequency = <166000000>;
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status = "disabled";
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};
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};
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risaf2: risaf@420b0000 {
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compatible = "st,stm32-risaf";
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reg = <0x420b0000 0x1000>;
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clocks = <&rcc CK_KER_OSPI1>;
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status = "disabled";
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};
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risaf4: risaf@420d0000 {
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compatible = "st,stm32-risaf";
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reg = <0x420d0000 0x1000>;
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clocks = <&rcc CK_BUS_RISAF4>;
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status = "disabled";
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};
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bsec: efuse@44000000 {
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compatible = "st,stm32mp25-bsec";
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reg = <0x44000000 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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uid_otp: uid-otp@14 {
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reg = <0x14 0xc>;
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};
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part_number_otp: part-number-otp@24 {
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reg = <0x24 0x4>;
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};
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nand_otp: otp16@40 {
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reg = <0x40 0x4>;
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};
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lifecycle2_otp: otp18@48 {
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reg = <0x48 0x4>;
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};
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nand2_otp: otp20@50 {
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reg = <0x50 0x4>;
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};
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rev_otp@198 {
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reg = <0x198 0x4>;
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};
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package_otp: package-otp@1e8 {
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reg = <0x1e8 0x1>;
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};
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hconf1_otp: otp124@1f0 {
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reg = <0x1f0 0x4>;
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};
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pkh_otp: otp144@240 {
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reg = <0x240 0x20>;
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};
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oem_fip_enc_key: otp260@410 {
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reg = <0x410 0x20>;
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};
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};
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rcc: clock-controller@44200000 {
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compatible = "st,stm32mp25-rcc";
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reg = <0x44200000 0x10000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pwr: pwr@44210000 {
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compatible = "st,stm32mp25-pwr";
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reg = <0x44210000 0x400>;
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vddio1: vddio1 {
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regulator-name = "vddio1";
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};
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vddio2: vddio2 {
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regulator-name = "vddio2";
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};
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vddio3: vddio3 {
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regulator-name = "vddio3";
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};
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vddio4: vddio4 {
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regulator-name = "vddio4";
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};
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vddio: vddio {
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regulator-name = "vddio";
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};
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};
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syscfg: syscon@44230000 {
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compatible = "st,stm32mp25-syscfg", "syscon";
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reg = <0x44230000 0x10000>;
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};
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tamp: tamp@46010000 {
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compatible = "st,stm32mp25-tamp";
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reg = <0x46010000 0x400>;
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clocks = <&rcc CK_BUS_RTC>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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nvram: nvram@46010100 {
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compatible = "st,stm32mp25-tamp-nvram";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x46010100 0x200>;
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stop2_entrypoint: tamp-bkp@2c {
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reg = <0x2c 0x4>;
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};
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fwu_info: tamp-bkp@c0 {
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/* see firmware update info feature */
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reg = <0xc0 0x4>;
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};
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boot_mode: tamp-bkp@180 {
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reg = <0x180 0x4>;
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};
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};
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boot_info: boot-info {
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compatible = "st,stm32mp-bootinfo";
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nvmem-cells = <&boot_mode>, <&fwu_info>, <&stop2_entrypoint>;
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nvmem-cell-names = "boot-mode", "fwu-info", "stop2-entrypoint";
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};
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};
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ddr: ddr@48040000 {
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compatible = "st,stm32mp2-ddr";
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reg = <0x48040000 0x10000>,
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<0x48c00000 0x400000>;
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status = "okay";
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};
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fmc: memory-controller@48200000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "st,stm32mp25-fmc2-ebi";
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reg = <0x48200000 0x400>;
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clocks = <&rcc CK_KER_FMC>;
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resets = <&rcc FMC_R>;
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status = "disabled";
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ranges = <0 0 0x70000000 0x04000000>, /* EBI CS 1 */
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<1 0 0x74000000 0x04000000>, /* EBI CS 2 */
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<2 0 0x78000000 0x04000000>, /* EBI CS 3 */
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<3 0 0x7c000000 0x04000000>, /* EBI CS 4 */
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<4 0 0x48810000 0x00001000>; /* NAND */
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nand-controller@4,0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32mp25-fmc2-nfc";
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reg = <4 0x0000 0x10>,
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<4 0x0090 0x10>,
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<4 0x00a0 0x10>,
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<4 0x0400 0x10>,
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<4 0x0490 0x10>,
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<4 0x04a0 0x10>,
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<4 0x0800 0x10>,
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<4 0x0890 0x10>,
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<4 0x08a0 0x10>,
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<4 0x0c00 0x10>,
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<4 0x0c90 0x10>,
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<4 0x0ca0 0x10>;
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interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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/*
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* Break node order to solve dependency probe issue between
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* pinctrl and exti.
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*/
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pinctrl: pinctrl@44240000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp257-pinctrl";
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ranges = <0 0x44240000 0xa0400>;
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gpioa: gpio@44240000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x0 0x400>;
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clocks = <&rcc CK_BUS_GPIOA>;
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st,bank-name = "GPIOA";
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status = "disabled";
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};
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gpiob: gpio@44250000 {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x10000 0x400>;
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clocks = <&rcc CK_BUS_GPIOB>;
|
|
st,bank-name = "GPIOB";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioc: gpio@44260000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x20000 0x400>;
|
|
clocks = <&rcc CK_BUS_GPIOC>;
|
|
st,bank-name = "GPIOC";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiod: gpio@44270000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x30000 0x400>;
|
|
clocks = <&rcc CK_BUS_GPIOD>;
|
|
st,bank-name = "GPIOD";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioe: gpio@44280000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x40000 0x400>;
|
|
clocks = <&rcc CK_BUS_GPIOE>;
|
|
st,bank-name = "GPIOE";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiof: gpio@44290000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x50000 0x400>;
|
|
clocks = <&rcc CK_BUS_GPIOF>;
|
|
st,bank-name = "GPIOF";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiog: gpio@442a0000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x60000 0x400>;
|
|
clocks = <&rcc CK_BUS_GPIOG>;
|
|
st,bank-name = "GPIOG";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioh: gpio@442b0000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x70000 0x400>;
|
|
clocks = <&rcc CK_BUS_GPIOH>;
|
|
st,bank-name = "GPIOH";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioi: gpio@442c0000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x80000 0x400>;
|
|
clocks = <&rcc CK_BUS_GPIOI>;
|
|
st,bank-name = "GPIOI";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpioj: gpio@442d0000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x90000 0x400>;
|
|
clocks = <&rcc CK_BUS_GPIOJ>;
|
|
st,bank-name = "GPIOJ";
|
|
status = "disabled";
|
|
};
|
|
|
|
gpiok: gpio@442e0000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0xa0000 0x400>;
|
|
clocks = <&rcc CK_BUS_GPIOK>;
|
|
st,bank-name = "GPIOK";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pinctrl_z: pinctrl@46200000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "st,stm32mp257-z-pinctrl";
|
|
ranges = <0 0x46200000 0x400>;
|
|
|
|
gpioz: gpio@46200000 {
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0 0x400>;
|
|
clocks = <&rcc CK_BUS_GPIOZ>;
|
|
st,bank-name = "GPIOZ";
|
|
st,bank-ioport = <11>;
|
|
status = "disabled";
|
|
};
|
|
|
|
};
|
|
};
|
|
};
|