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Add the required device tree files for STM32MP215F-DK board support. Change-Id: Iae607cf9a4308750c18dbba40e29ba483b1f6dcb Signed-off-by: Yann Gautier <yann.gautier@st.com>
89 lines
1.7 KiB
Devicetree
89 lines
1.7 KiB
Devicetree
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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/*
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* Copyright (c) 2026, STMicroelectronics - All Rights Reserved
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* Author: Loic Pallardy loic.pallardy@foss.st.com for STMicroelectronics.
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*/
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/*
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* stm32mp215f Clock tree device tree configuration
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* Project : open
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* Generated by XLmx tool version 2.2 - 10/2/2024 3:58:35 PM
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*/
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&clk_hse {
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clock-frequency = <40000000>;
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};
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&clk_hsi {
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clock-frequency = <64000000>;
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};
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&clk_lse {
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clock-frequency = <32768>;
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};
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&clk_lsi {
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clock-frequency = <32000>;
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};
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&clk_msi {
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clock-frequency = <16000000>;
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};
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&rcc {
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st,busclk = <
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DIV_CFG(DIV_LSMCU, 1)
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DIV_CFG(DIV_APB1, 0)
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DIV_CFG(DIV_APB2, 0)
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DIV_CFG(DIV_APB3, 0)
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DIV_CFG(DIV_APB4, 0)
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DIV_CFG(DIV_APB5, 0)
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DIV_CFG(DIV_APBDBG, 0)
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>;
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st,flexgen = <
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FLEXGEN_CFG(0, XBAR_SRC_PLL4, 0, 3)
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FLEXGEN_CFG(1, XBAR_SRC_PLL4, 0, 5)
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FLEXGEN_CFG(2, XBAR_SRC_PLL4, 0, 1)
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FLEXGEN_CFG(4, XBAR_SRC_PLL4, 0, 3)
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FLEXGEN_CFG(5, XBAR_SRC_PLL4, 0, 2)
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FLEXGEN_CFG(8, XBAR_SRC_HSI_KER, 0, 0)
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FLEXGEN_CFG(51, XBAR_SRC_PLL4, 0, 5)
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FLEXGEN_CFG(52, XBAR_SRC_PLL4, 0, 5)
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FLEXGEN_CFG(58, XBAR_SRC_HSE_KER, 0, 1)
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FLEXGEN_CFG(63, XBAR_SRC_PLL4, 0, 2)
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>;
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st,kerclk = <
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MUX_CFG(MUX_USB2PHY1, MUX_USB2PHY1_FLEX57)
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MUX_CFG(MUX_USB2PHY2, MUX_USB2PHY2_FLEX58)
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>;
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pll1: st,pll-1 {
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st,pll = <&pll1_cfg_1200MHz>;
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pll1_cfg_1200MHz: pll1-cfg-1200MHz {
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cfg = <30 1 1 1>;
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src = <MUX_CFG(MUX_MUXSEL5, MUXSEL_HSE)>;
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};
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};
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pll2: st,pll-2 {
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st,pll = <&pll2_cfg_400MHz>;
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pll2_cfg_400MHz: pll2-cfg-400MHz {
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cfg = <20 1 1 2>;
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src = <MUX_CFG(MUX_MUXSEL6, MUXSEL_HSE)>;
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};
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};
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pll4: st,pll-4 {
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st,pll = <&pll4_cfg_1200MHz>;
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pll4_cfg_1200MHz: pll4-cfg-1200MHz {
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cfg = <30 1 1 1>;
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src = <MUX_CFG(MUX_MUXSEL0, MUXSEL_HSE)>;
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};
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};
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};
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