mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2026-07-04 08:58:40 +00:00
Boyan Karatotev
70a6541a70
Keeping everything feature related in arch_features.mk is very
convenient but is subtly broken - platforms occasionally make decision
on whether a feature was enabled on the commandline. This is usually
done with a line like `ifneq (${ENABLE_FEAT_ABC},0)` which will pass if
the flag is unset, very much the opposite of what should happen. The
easiest way to fix this is to set defaults prior to platform.mk, i.e. in
defaults.mk.
Change-Id: I6a3a9f287045b57a66c30cbda77898b2774d3da9
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
830 lines
22 KiB
Makefile
830 lines
22 KiB
Makefile
#
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# Copyright (c) 2016-2026, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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# Default, static values for build variables, listed in alphabetic order.
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# Dependencies between build options, if any, are handled in the top-level
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# Makefile, after this file is included. This ensures that the former is better
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# poised to handle dependencies, as all build variables would have a default
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# value by then.
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# Warning level to give to the compiler
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W := 0
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# Use T32 by default
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AARCH32_INSTRUCTION_SET := T32
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# The AArch32 Secure Payload to be built as BL32 image
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AARCH32_SP := none
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# The Target build architecture. Supported values are: aarch64, aarch32.
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ARCH := aarch64
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# ARM Architecture feature modifiers: none by default
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ARM_ARCH_FEATURE := none
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# ARM Architecture major and minor versions: 8.0 by default.
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ARM_ARCH_MAJOR := 8
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ARM_ARCH_MINOR := 0
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# Base commit to perform code check on
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BASE_COMMIT := origin/master
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# Execute BL2 at EL3
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RESET_TO_BL2 := 0
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# Only use SP packages if SP layout JSON is defined
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BL2_ENABLE_SP_LOAD := 0
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# BL2 image is stored in XIP memory, for now, this option is only supported
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# when RESET_TO_BL2 is 1.
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BL2_IN_XIP_MEM := 0
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# Do dcache invalidate upon BL2 entry at EL3
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BL2_INV_DCACHE := 1
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# Select the branch protection features to use.
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BRANCH_PROTECTION := 0
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# By default, consider that the platform may release several CPUs out of reset.
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# The platform Makefile is free to override this value.
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COLD_BOOT_SINGLE_CPU := 0
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# Flag to compile in coreboot support code. Exclude by default. The coreboot
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# Makefile system will set this when compiling TF as part of a coreboot image.
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COREBOOT := 0
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# For Chain of Trust
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CREATE_KEYS := 1
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# Build flag to include AArch32 registers in cpu context save and restore during
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# world switch. This flag must be set to 0 for AArch64-only platforms.
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CTX_INCLUDE_AARCH32_REGS := 1
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# Include FP registers in cpu context
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CTX_INCLUDE_FPREGS := 0
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# Include SVE registers in cpu context
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CTX_INCLUDE_SVE_REGS := 0
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# Debug build
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DEBUG := 0
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# By default disable authenticated decryption support.
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DECRYPTION_SUPPORT := none
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# Build platform
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DEFAULT_PLAT := fvp
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# Disable the generation of the binary image (ELF only).
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DISABLE_BIN_GENERATION := 0
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# Enable capability to disable authentication dynamically. Only meant for
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# development platforms.
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DYN_DISABLE_AUTH := 0
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# Enable the SIMD crypto extension feature. The flags suppose to be in
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# arch_features.mk but since mbedtls_common.mk is included before arch_features.mk,
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# so this flag has to be defined here.
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ENABLE_FEAT_CRYPTO := 0
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# Enable the SIMD SHA3 crypto extension feature.
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ENABLE_FEAT_CRYPTO_SHA3 := 0
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# Enable the Maximum Power Mitigation Mechanism on supporting cores.
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ENABLE_MPMM := 0
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# Flag to Enable Position Independant support (PIE)
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ENABLE_PIE := 0
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# Flag to enable Performance Measurement Framework
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ENABLE_PMF := 0
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# Flag to enable PSCI STATs functionality
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ENABLE_PSCI_STAT := 0
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# Flag to enable runtime instrumentation using PMF
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ENABLE_RUNTIME_INSTRUMENTATION := 0
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# Flag to enable stack corruption protection
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ENABLE_STACK_PROTECTOR := 0
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# Flag to enable exception handling in EL3
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EL3_EXCEPTION_HANDLING := 0
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# Flag to include all errata for all CPUs TF-A implements workarounds for
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# Its supposed to be used only for testing.
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ENABLE_ERRATA_ALL := 0
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# By default BL31 encryption disabled
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ENCRYPT_BL31 := 0
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# By default BL32 encryption disabled
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ENCRYPT_BL32 := 0
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# Default dummy firmware encryption key
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ENC_KEY := 1234567890abcdef1234567890abcdef1234567890abcdef1234567890abcdef
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# Default dummy nonce for firmware encryption
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ENC_NONCE := 1234567890abcdef12345678
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# Build flag to treat usage of deprecated platform and framework APIs as error.
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ERROR_DEPRECATED := 0
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# Fault injection support
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FAULT_INJECTION_SUPPORT := 0
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# Flag to enable architectural features detection mechanism
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FEATURE_DETECTION := 0
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# Byte alignment that each component in FIP is aligned to
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FIP_ALIGN := 0
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# Default FIP file name
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FIP_NAME := fip.bin
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# Default FWU_FIP file name
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FWU_FIP_NAME := fwu_fip.bin
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# Default BL2 FIP file name
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BL2_FIP_NAME := bl2_fip.bin
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# By default firmware encryption with SSK
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FW_ENC_STATUS := 0
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# For Chain of Trust
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GENERATE_COT := 0
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# Default number of 512 blocks per bitlock
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RME_GPT_BITLOCK_BLOCK := 1
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# Default maximum size of GPT contiguous block
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RME_GPT_MAX_BLOCK := 512
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# Hint platform interrupt control layer that Group 0 interrupts are for EL3. By
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# default, they are for Secure EL1.
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GICV2_G0_FOR_EL3 := 0
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# Generic implementation of a GICvX driver
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USE_GIC_DRIVER := 0
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# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled
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# by lower ELs.
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HANDLE_EA_EL3_FIRST_NS := 0
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# Enable Handoff protocol using transfer lists
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TRANSFER_LIST := 0
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# Enable HOB list to generate boot information
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HOB_LIST := 0
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# Enables support for the gcc compiler option "-mharden-sls=all".
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# By default, disables all SLS hardening.
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HARDEN_SLS := 0
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# Secure hash algorithm flag, accepts 3 values: sha256, sha384 and sha512.
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# The default value is sha256.
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HASH_ALG := sha256
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# Whether system coherency is managed in hardware, without explicit software
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# operations.
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HW_ASSISTED_COHERENCY := 0
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# Flag to enable trapping of implementation defined sytem registers
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IMPDEF_SYSREG_TRAP := 0
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# Set the default algorithm for the generation of Trusted Board Boot keys
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KEY_ALG := rsa
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# Set the default key size in case KEY_ALG is rsa
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ifeq ($(KEY_ALG),rsa)
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KEY_SIZE := 2048
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endif
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# Option to build TF with Measured Boot support
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MEASURED_BOOT := 0
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# Option to build TF with Discrete TPM support
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DISCRETE_TPM := 0
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# Option to enable the DICE Protection Environmnet as a Measured Boot backend
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DICE_PROTECTION_ENVIRONMENT :=0
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# NS timer register save and restore (deprecated)
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NS_TIMER_SWITCH := 0
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# Include lib/libc in the final image
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OVERRIDE_LIBC := 0
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# Build PL011 UART driver in minimal generic UART mode
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PL011_GENERIC_UART := 0
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# By default, consider that the platform's reset address is not programmable.
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# The platform Makefile is free to override this value.
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PROGRAMMABLE_RESET_ADDRESS := 0
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# Flag used to choose the power state format: Extended State-ID or Original
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PSCI_EXTENDED_STATE_ID := 0
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# Enable PSCI OS-initiated mode support
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PSCI_OS_INIT_MODE := 0
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# SMCCC_ARCH_FEATURE_AVAILABILITY support
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ARCH_FEATURE_AVAILABILITY := 0
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# By default, BL1 acts as the reset handler, not BL31
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RESET_TO_BL31 := 0
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# For Chain of Trust
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SAVE_KEYS := 0
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# Software Delegated Exception support
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SDEI_SUPPORT := 0
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# Number of UUIDs allowed for a physical partition
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SPMC_AT_EL3_PARTITION_MAX_UUIDS := 4
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# True Random Number firmware Interface support
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TRNG_SUPPORT := 0
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# Check to see if Errata ABI is supported
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ERRATA_ABI_SUPPORT := 0
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# Check to enable Errata ABI for platforms with non-arm interconnect
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ERRATA_NON_ARM_INTERCONNECT := 0
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# SMCCC PCI support
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SMC_PCI_SUPPORT := 0
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# Whether code and read-only data should be put on separate memory pages. The
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# platform Makefile is free to override this value.
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SEPARATE_CODE_AND_RODATA := 0
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# Put NOBITS sections (.bss, stacks, page tables, and coherent memory) in a
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# separate memory region, which may be discontiguous from the rest of BL31.
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SEPARATE_NOBITS_REGION := 0
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# Put BL2 NOLOAD sections (.bss, stacks, page tables) in a separate memory
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# region, platform Makefile is free to override this value.
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SEPARATE_BL2_NOLOAD_REGION := 0
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# Put RW DATA sections (.rwdata) in a separate memory region, which may be
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# discontiguous from the rest of BL31.
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SEPARATE_RWDATA_REGION := 0
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# Put SIMD context data structures in a separate memory region. Platforms
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# have the choice to put it outside of default BSS region of EL3 firmware.
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SEPARATE_SIMD_SECTION := 0
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# If the BL31 image initialisation code is recalimed after use for the secondary
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# cores stack
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RECLAIM_INIT_CODE := 0
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# SPD choice
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SPD := none
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# Enable the Management Mode (MM)-based Secure Partition Manager implementation
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SPM_MM := 0
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# Use the FF-A SPMC implementation in EL3.
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SPMC_AT_EL3 := 0
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# Enable SEL0 SP when SPMC is enabled at EL3
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SPMC_AT_EL3_SEL0_SP :=0
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# Use SPM at S-EL2 as a default config for SPMD
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SPMD_SPM_AT_SEL2 := 1
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# Flag to introduce an infinite loop in BL1 just before it exits into the next
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# image. This is meant to help debugging the post-BL2 phase.
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SPIN_ON_BL1_EXIT := 0
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# Flags to build TF with Trusted Boot support
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TRUSTED_BOARD_BOOT := 0
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# Build option to choose whether Trusted Firmware uses Coherent memory or not.
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USE_COHERENT_MEM := 1
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# Build option to add debugfs support
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USE_DEBUGFS := 0
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# Build option to enable passing the FDT in x0 to BL33, following the kernel
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# convention.
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USE_KERNEL_DT_CONVENTION := 0
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# Build option to fconf based io
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ARM_IO_IN_DTB := 0
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# Build option to support SDEI through fconf
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SDEI_IN_FCONF := 0
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# Build option to support Secure Interrupt descriptors through fconf
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SEC_INT_DESC_IN_FCONF := 0
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# Build option to choose whether Trusted Firmware uses library at ROM
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USE_ROMLIB := 0
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# Build option to choose whether the xlat tables of BL images can be read-only.
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# Note that this only serves as a higher level option to PLAT_RO_XLAT_TABLES,
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# which is the per BL-image option that actually enables the read-only tables
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# API. The reason for having this additional option is to have a common high
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# level makefile where we can check for incompatible features/build options.
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ALLOW_RO_XLAT_TABLES := 0
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# Chain of trust.
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COT := tbbr
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# Use tbbr_oid.h instead of platform_oid.h
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USE_TBBR_DEFS := 1
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# Whether to enable D-Cache early during warm boot. This is usually
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# applicable for platforms wherein interconnect programming is not
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# required to enable cache coherency after warm reset (eg: single cluster
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# platforms).
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WARMBOOT_ENABLE_DCACHE_EARLY := 0
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# Default SVE vector length to maximum architected value
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SVE_VECTOR_LEN := 2048
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SANITIZE_UB := off
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# Enable Link Time Optimization
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ENABLE_LTO := 0
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# This option will include EL2 registers in cpu context save and restore during
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# EL2 firmware entry/exit. Internal flag not meant for direct setting.
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# Use SPD=spmd and SPMD_SPM_AT_SEL2=1 or ENABLE_RMM=1 to enable
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# CTX_INCLUDE_EL2_REGS.
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CTX_INCLUDE_EL2_REGS := 0
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# Select workaround for AT speculative behaviour.
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ERRATA_SPECULATIVE_AT := 0
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# Trap RAS error record access from Non secure
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RAS_TRAP_NS_ERR_REC_ACCESS := 0
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# Build option to create cot descriptors using fconf
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COT_DESC_IN_DTB := 0
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# Build option to provide OpenSSL directory path
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OPENSSL_DIR := /usr
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# Select the openssl binary provided in OPENSSL_DIR variable
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ifeq ("$(wildcard ${OPENSSL_DIR}/bin)", "")
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OPENSSL_BIN_PATH = ${OPENSSL_DIR}/apps
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else
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OPENSSL_BIN_PATH = ${OPENSSL_DIR}/bin
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endif
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# Build option to use the SP804 timer instead of the generic one
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USE_SP804_TIMER := 0
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# Build option to define number of firmware banks, used in firmware update
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# metadata structure.
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NR_OF_FW_BANKS := 2
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# Build option to define number of images in firmware bank, used in firmware
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# update metadata structure.
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NR_OF_IMAGES_IN_FW_BANK := 1
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# Disable Firmware update support by default
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PSA_FWU_SUPPORT := 0
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# Enable image description in FWU metadata by default when PSA_FWU_SUPPORT
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# is enabled.
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ifeq ($(PSA_FWU_SUPPORT),1)
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PSA_FWU_METADATA_FW_STORE_DESC := 1
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else
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PSA_FWU_METADATA_FW_STORE_DESC := 0
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endif
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# Dynamic Root of Trust for Measurement support
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DRTM_SUPPORT := 0
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# Check platform if cache management operations should be performed.
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# Disabled by default.
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CONDITIONAL_CMO := 0
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# By default, disable SPMD Logical partitions
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ENABLE_SPMD_LP := 0
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# By default, disable PSA crypto (use MbedTLS legacy crypto API).
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PSA_CRYPTO := 0
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# getc() support from the console(s).
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# Disabled by default because it constitutes an attack vector into TF-A. It
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# should only be enabled if there is a use case for it.
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ENABLE_CONSOLE_GETC := 0
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# Build option to disable EL2 when it is not used.
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# Most platforms switch from EL3 to NS-EL2 and hence the unused NS-EL2
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# functions must be enabled by platforms if they require it.
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# Disabled by default.
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INIT_UNUSED_NS_EL2 := 0
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# Disable including MPAM EL2 registers in context by default since currently
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# it's only enabled for NS world
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CTX_INCLUDE_MPAM_REGS := 0
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# Enable context memory usage reporting during BL31 setup.
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PLATFORM_REPORT_CTX_MEM_USE := 0
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# Request a custom addition to the BL31 linker script
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PLAT_EXTRA_LD_SCRIPT := 0
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# Enable early console
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EARLY_CONSOLE := 0
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# Allow platforms to save/restore DSU PMU registers over a power cycle.
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# Disabled by default and must be enabled by individual platforms.
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PRESERVE_DSU_PMU_REGS := 0
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# Flag to enable an RME payload
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ENABLE_RMM := 0
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# Enable RMMD to forward attestation requests from RMM to EL3.
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RMMD_ENABLE_EL3_TOKEN_SIGN := 0
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# Enable RMMD to program and manage IDE Keys at the PCIe Root Port(RP).
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# This flag is temporary and it is expected once the interface is
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# finalized, this flag will be removed.
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RMMD_ENABLE_IDE_KEY_PROG := 0
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# Enable RMM v1.x compatibility mode
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RMM_V1_COMPAT := 0
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# Live firmware activation support
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LFA_SUPPORT := 0
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# Enable support for arm DSU driver.
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USE_DSU_DRIVER := 0
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# Define the separation of BL2 flag, by default it is disabled.
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SEPARATE_BL2_FIP := 0
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# Disable NUMA awareness for per-CPU framework by default. Platforms should
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# enable this feature by setting PLATFORM_NODE_COUNT > 1
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PLATFORM_NODE_COUNT := 1
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# Support for live activation of SPs managed by S-EL2 SPMC
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SUPPORT_SP_LIVE_ACTIVATION := 0
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# Negative I/O test: intentionally report a short read for a selected
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# image_id. Test/CI only. Do not enable in production builds.
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TEST_IO_SHORT_READ_FI := 0
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TEST_IO_SHORT_READ_FI_IMAGE_ID := 0
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# Enable the FIRME interface.
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FIRME_SUPPORT := 0
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# Flag to enable the spinlock implementation variant using the FEAT_LSE
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# compare-and-swap instruction.
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USE_SPINLOCK_CAS ?= 0
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#----
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# 8.1
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#----
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# Flag to enable access to Privileged Access Never bit of PSTATE.
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ENABLE_FEAT_PAN ?= 0
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# Flag to enable Virtualization Host Extensions.
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ENABLE_FEAT_VHE ?= 0
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#----
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# 8.2
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#----
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# Enable RAS Support.
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ENABLE_FEAT_RAS ?= 0
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#----
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# 8.3
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#----
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# Flag to enable Pointer Authentication. Internal flag not meant for
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# direct setting. Use BRANCH_PROTECTION to enable PAUTH.
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ENABLE_PAUTH ?= 0
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# FEAT_PAUTH_LR is an optional architectural feature, so this flag must be set
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# manually in addition to the BRANCH_PROTECTION flag which is used for other
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# branch protection and pointer authentication features.
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ENABLE_FEAT_PAUTH_LR ?= 0
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# Include pointer authentication (ARMv8.3-PAuth) registers in cpu context. This
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# must be set to 1 if the platform wants to use this feature in the Secure
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# world. It is not necessary for use in the Non-secure world.
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CTX_INCLUDE_PAUTH_REGS ?= 0
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#----
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# 8.4
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#----
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# Flag to enable Secure EL-2 feature.
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ENABLE_FEAT_SEL2 ?= 0
|
|
|
|
# By default, disable trace filter control register access to lower non-secure
|
|
# exception levels, i.e. NS-EL2, or NS-EL1 if NS-EL2 is implemented, but
|
|
# trace filter control register access is unused if FEAT_TRF is implemented.
|
|
ENABLE_TRF_FOR_NS ?= 0
|
|
|
|
# Flag to enable Data Independent Timing instructions.
|
|
ENABLE_FEAT_DIT ?= 0
|
|
|
|
#----
|
|
# 8.5
|
|
#----
|
|
|
|
# Flag to enable Branch Target Identification.
|
|
# Internal flag not meant for direct setting.
|
|
# Use BRANCH_PROTECTION to enable BTI.
|
|
ENABLE_BTI ?= 0
|
|
|
|
# Flag to enable access to the Random Number Generator registers.
|
|
ENABLE_FEAT_RNG ?= 0
|
|
|
|
# Flag to enable Speculation Barrier Instruction.
|
|
ENABLE_FEAT_SB ?= 0
|
|
|
|
#----
|
|
# 8.6
|
|
#----
|
|
|
|
# Flag to enable access to the CNTPOFF_EL2 register.
|
|
ENABLE_FEAT_ECV ?= 0
|
|
|
|
# Flag to enable access to the HDFGRTR_EL2 register.
|
|
ENABLE_FEAT_FGT ?= 0
|
|
|
|
#----
|
|
# 8.7
|
|
#----
|
|
|
|
# Flag to enable access to the HCRX_EL2 register by setting SCR_EL3.HXEn.
|
|
ENABLE_FEAT_HCX ?= 0
|
|
|
|
#----
|
|
# 8.8
|
|
#----
|
|
|
|
# Flag to enable FEAT_MOPS (Standardization of Memory operations)
|
|
# when INIT_UNUSED_NS_EL2 = 1
|
|
ENABLE_FEAT_MOPS ?= 0
|
|
|
|
#----
|
|
# 8.9
|
|
#----
|
|
|
|
# Flag to enable access to TCR2 (FEAT_TCR2).
|
|
ENABLE_FEAT_TCR2 ?= 0
|
|
|
|
# Flag to enable access to SCTLR2 (FEAT_SCTLR2).
|
|
ENABLE_FEAT_SCTLR2 ?= 0
|
|
|
|
#
|
|
################################################################################
|
|
# Optional Features defaulted to 0 or 2, if they are not enabled from
|
|
# build option. Can also be disabled or enabled by platform if needed.
|
|
################################################################################
|
|
#
|
|
|
|
#----
|
|
# 8.0
|
|
#----
|
|
|
|
# Flag to enable support for clrbhb instruction.
|
|
ENABLE_FEAT_CLRBHB ?= 0
|
|
|
|
# Flag to enable CSV2_2 extension.
|
|
ENABLE_FEAT_CSV2_2 ?= 0
|
|
|
|
# Flag to enable CSV2_3 extension. FEAT_CSV2_3 enables access to the
|
|
# SCXTNUM_ELx register.
|
|
ENABLE_FEAT_CSV2_3 ?= 0
|
|
|
|
# By default, disable access of trace system registers from NS lower
|
|
# ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused if
|
|
# system register trace is implemented. This feature is available if
|
|
# trace unit such as ETMv4.x, This feature is OPTIONAL and is only
|
|
# permitted in Armv8 implementations.
|
|
ENABLE_SYS_REG_TRACE_FOR_NS ?= 0
|
|
|
|
#----
|
|
# 8.2
|
|
#----
|
|
|
|
# Build option to enable/disable the Statistical Profiling Extension,
|
|
# keep it enabled by default for AArch64.
|
|
ifeq (${ARCH},aarch64)
|
|
ENABLE_SPE_FOR_NS ?= 2
|
|
else ifeq (${ARCH},aarch32)
|
|
ENABLE_SPE_FOR_NS := 0
|
|
endif
|
|
|
|
# Enable SVE for non-secure world by default.
|
|
ifeq (${ARCH},aarch64)
|
|
ENABLE_SVE_FOR_NS ?= 2
|
|
# SVE is only supported on AArch64 so disable it on AArch32.
|
|
else ifeq (${ARCH},aarch32)
|
|
ENABLE_SVE_FOR_NS := 0
|
|
endif
|
|
|
|
#----
|
|
# 8.4
|
|
#----
|
|
|
|
# Feature flags for supporting Activity monitor extensions.
|
|
ENABLE_FEAT_AMU ?= 0
|
|
ENABLE_AMU_AUXILIARY_COUNTERS ?= 0
|
|
AMU_RESTRICT_COUNTERS ?= 1
|
|
|
|
# Build option to enable MPAM for lower ELs.
|
|
# Enabling it by default
|
|
ifeq (${ARCH},aarch64)
|
|
ENABLE_FEAT_MPAM ?= 2
|
|
else ifeq (${ARCH},aarch32)
|
|
ENABLE_FEAT_MPAM := 0
|
|
endif
|
|
|
|
# Include nested virtualization control (Armv8.4-NV) registers in cpu context.
|
|
# This must be set to 1 if architecture implements Nested Virtualization
|
|
# Extension and platform wants to use this feature in the Secure world.
|
|
CTX_INCLUDE_NEVE_REGS ?= 0
|
|
|
|
#----
|
|
# 8.5
|
|
#----
|
|
|
|
# Flag to enable support for EL3 trapping of reads of the RNDR and RNDRRS
|
|
# registers, by setting SCR_EL3.TRNDR.
|
|
ENABLE_FEAT_RNG_TRAP ?= 0
|
|
|
|
# Enable FEAT_MTE2. This must be set to 1 if the platform wants
|
|
# to use this feature and is enabled at ELX.
|
|
ENABLE_FEAT_MTE2 ?= 0
|
|
|
|
#----
|
|
# 8.6
|
|
#----
|
|
|
|
# Flag to enable AMUv1p1 extension.
|
|
ENABLE_FEAT_AMUv1p1 ?= 0
|
|
|
|
# Flag to enable delayed trapping of WFE instruction (FEAT_TWED).
|
|
ENABLE_FEAT_TWED ?= 0
|
|
|
|
# In v8.6+ platforms with delayed trapping of WFE being supported
|
|
# via FEAT_TWED, this flag takes the delay value to be set in the
|
|
# SCR_EL3.TWEDEL(4bit) field, when FEAT_TWED is implemented.
|
|
# By default it takes 0, and need to be updated by the platforms.
|
|
TWED_DELAY ?= 0
|
|
|
|
# Disable MTPMU if FEAT_MTPMU is supported.
|
|
DISABLE_MTPMU ?= 0
|
|
|
|
# Flag to enable FEAT_FGT2 (Fine Granular Traps 2)
|
|
ENABLE_FEAT_FGT2 ?= 0
|
|
|
|
# LoadStore64Bytes extension using the ACCDATA_EL1 system register
|
|
ENABLE_FEAT_LS64_ACCDATA ?= 0
|
|
|
|
#----
|
|
# 8.8
|
|
#----
|
|
|
|
# Flag to enable FEAT_THE (Translation Hardening Extension)
|
|
ENABLE_FEAT_THE ?= 0
|
|
|
|
#----
|
|
# 8.9
|
|
#----
|
|
|
|
# Flag to enable access to Stage 2 Permission Indirection (FEAT_S2PIE).
|
|
ENABLE_FEAT_S2PIE ?= 0
|
|
|
|
# Flag to enable access to Stage 1 Permission Indirection (FEAT_S1PIE).
|
|
ENABLE_FEAT_S1PIE ?= 0
|
|
|
|
# Flag to enable access to Stage 2 Permission Overlay (FEAT_S2POE).
|
|
ENABLE_FEAT_S2POE ?= 0
|
|
|
|
# Flag to enable access to Stage 1 Permission Overlay (FEAT_S1POE).
|
|
ENABLE_FEAT_S1POE ?= 0
|
|
|
|
# Flag to enable access to Arm v8.9 Debug extension
|
|
ENABLE_FEAT_DEBUGV8P9 ?= 0
|
|
|
|
# AIE extension using the (A)MAIR2 system registers
|
|
ENABLE_FEAT_AIE ?= 0
|
|
|
|
# PFAR extension using the PFAR system registers
|
|
ENABLE_FEAT_PFAR ?= 0
|
|
|
|
#-------------------------------------------------------------
|
|
# Non-standard feature
|
|
#-------------------------------------------------------------
|
|
ENABLE_FEAT_MORELLO ?= 0
|
|
|
|
#----
|
|
# 9.0
|
|
#----
|
|
|
|
# Scalable Matrix Extension for non-secure world.
|
|
ENABLE_SME_FOR_NS ?= 0
|
|
|
|
# Scalable Vector Extension for secure world.
|
|
ENABLE_SVE_FOR_SWD ?= 0
|
|
|
|
# By default, disable access of trace buffer control registers from NS
|
|
# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
|
|
# if FEAT_TRBE is implemented.
|
|
# Note FEAT_TRBE is only supported on AArch64 - therefore do not enable in
|
|
# AArch32.
|
|
ifeq (${ARCH},aarch64)
|
|
ENABLE_TRBE_FOR_NS ?= 0
|
|
else ifeq (${ARCH},aarch32)
|
|
ifneq ($(or $(ENABLE_TRBE_FOR_NS),0),0)
|
|
$(error ENABLE_TRBE_FOR_NS is not supported for AArch32)
|
|
else
|
|
ENABLE_TRBE_FOR_NS := 0
|
|
endif
|
|
endif
|
|
|
|
# Flag that enables hardware injection of undefined exceptions
|
|
ENABLE_FEAT_UINJ ?= 0
|
|
|
|
#----
|
|
# 9.2
|
|
#----
|
|
|
|
# Flag to enable Realm Management Extension (FEAT_RME).
|
|
ENABLE_FEAT_RME ?= 0
|
|
|
|
# Scalable Matrix Extension version 2 for non-secure world.
|
|
ENABLE_SME2_FOR_NS ?= 0
|
|
|
|
# Scalable Matrix Extension for secure world.
|
|
ENABLE_SME_FOR_SWD ?= 0
|
|
|
|
# By default, disable access to branch record buffer control registers from NS
|
|
# lower ELs i.e. NS-EL2, or NS-EL1 if NS-EL2 implemented but unused
|
|
# if FEAT_BRBE is implemented.
|
|
ENABLE_BRBE_FOR_NS ?= 0
|
|
|
|
# Flag to enable Floating point exception Mode Register Feature (FEAT_FPMR)
|
|
ENABLE_FEAT_FPMR ?= 0
|
|
|
|
# Flag to enable Memory Encryption Contexts (FEAT_MEC).
|
|
ENABLE_FEAT_MEC ?= 0
|
|
|
|
#----
|
|
# 9.3
|
|
#----
|
|
# Flag to enable access to Arm v9.3 FEAT_D128 extension
|
|
ENABLE_FEAT_D128 ?= 0
|
|
|
|
# Flag to enable access to GICv5 CPU interface extension (FEAT_GCIE)
|
|
ENABLE_FEAT_GCIE ?= 0
|
|
|
|
# Enables access to PE-side MPAM bandwidth controls (FEAT_MPAM_PE_BW_CTRL)
|
|
ENABLE_FEAT_MPAM_PE_BW_CTRL ?= 0
|
|
|
|
# Flag to enable Exception-based Event Profiling (FEAT_EBEP)
|
|
ENABLE_FEAT_EBEP ?= 0
|
|
|
|
#----
|
|
#9.4
|
|
#----
|
|
|
|
# Flag to enable FEAT_RME_GDI
|
|
ENABLE_FEAT_RME_GDI ?= 0
|
|
|
|
# Flag to enable access to Guarded Control Stack (FEAT_GCS).
|
|
ENABLE_FEAT_GCS ?= 0
|
|
|
|
# Flag to enable Fine Grained Write Traps (FEAT_FGWTE3) for EL3.
|
|
ENABLE_FEAT_FGWTE3 ?= 0
|
|
|
|
# Flag to enable checked pointer arithmetic (FEAT_CPA2) for EL3.
|
|
# We don't have a flag for FEAT_CPA since that has no effect on software
|
|
ENABLE_FEAT_CPA2 ?= 0
|
|
|
|
# Flag to enable Enhanced Software Step Extension (FEAT_STEP2)
|
|
ENABLE_FEAT_STEP2 ?= 0
|
|
|
|
# Flag to enable Hardware Dirty state tracking structure (FEAT_HDBSS).
|
|
ENABLE_FEAT_HDBSS ?= 0
|
|
|
|
# Flag to enable Hardening Address and Context Debug Banked State (FEAT_HACDBS).
|
|
ENABLE_FEAT_HACDBS ?= 0
|
|
|
|
#----
|
|
#9.6
|
|
#----
|
|
|
|
# Flag to enable trapping of ID registers to EL3
|
|
ENABLE_FEAT_IDTE3 ?= 0
|