mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2026-07-03 20:08:41 +00:00
Ryan Everett
743de0eab2
- Updated the data fs load address to align with the new memory layout requirements. - Defined and integrated the Buildroot memory layout into RAM. Change-Id: If6216150f4a0e97acda6ec4dbf5782ffc48bae23 Signed-off-by: Quoc Khanh Le <quockhanh.le@arm.com> Signed-off-by: Mohanprasath Ramamoorthy <mohanprasath.ramamoorthy@arm.com> Signed-off-by: Ryan Everett <ryan.everett@arm.com>
51 lines
1.1 KiB
Devicetree
51 lines
1.1 KiB
Devicetree
/*
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* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#define GIC_CTRL_ADDR 30000000
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#define GIC_GICR_OFFSET 0x1000000
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#define UART_OFFSET 0x10000
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/* 1440x3200@120 framebuffer */
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#define LCD_TIMING_CLK 836000000
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#define LCD_TIMING \
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clock-frequency = <LCD_TIMING_CLK>; \
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hactive = <1440>; \
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vactive = <3200>; \
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hfront-porch = <136>; \
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hback-porch = <296>; \
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hsync-len = <160>; \
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vfront-porch = <3>; \
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vback-porch = <217>; \
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vsync-len = <10>
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/ {
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chosen {
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stdout-path = "serial0:38400n8";
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};
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#if TC_FPGA_FS_IMG_IN_RAM
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reserved-memory {
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phram {
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/*
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* starting from base of DRAM2 reserve some memory,
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* the android/buildroot image will be side loaded to this location
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*/
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reg = <HI(TC_DRAM2_BASE) LO(TC_DRAM2_BASE)
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HI(DRAM_FS_SIZE) LO(DRAM_FS_SIZE)>;
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no-map;
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};
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};
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#endif /* TC_FPGA_FS_IMG_IN_RAM */
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ethernet: ethernet@ETHERNET_ADDR {
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compatible = "smsc,lan9115";
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phy-mode = "mii";
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};
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mmci: mmci@MMC_ADDR {
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non-removable;
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};
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};
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