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https://github.com/ARM-software/arm-trusted-firmware.git
synced 2026-07-05 03:38:39 +00:00
Soby MathewandDan Handley
8c5fe0b5b9
This patch moves the bakery locks out of coherent memory to normal memory. This implies that the lock information needs to be placed on a separate cache line for each cpu. Hence the bakery_lock_info_t structure is allocated in the per-cpu data so as to minimize memory wastage. A similar platform per-cpu data is introduced for the platform locks. As a result of the above changes, the bakery lock api is completely changed. Earlier, a reference to the lock structure was passed to the lock implementation. Now a unique-id (essentially an index into the per-cpu data array) and an offset into the per-cpu data for bakery_info_t needs to be passed to the lock implementation. Change-Id: I1e76216277448713c6c98b4c2de4fb54198b39e0
104 lines
3.3 KiB
C
104 lines
3.3 KiB
C
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch_helpers.h>
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#include <bakery_lock.h>
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#include <mmio.h>
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#include "juno_def.h"
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#include "juno_private.h"
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#include "mhu.h"
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/* SCP MHU secure channel registers */
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#define SCP_INTR_S_STAT 0x200
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#define SCP_INTR_S_SET 0x208
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#define SCP_INTR_S_CLEAR 0x210
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/* CPU MHU secure channel registers */
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#define CPU_INTR_S_STAT 0x300
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#define CPU_INTR_S_SET 0x308
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#define CPU_INTR_S_CLEAR 0x310
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#if IMAGE_BL31
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#if USE_COHERENT_MEM
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static bakery_lock_t mhu_secure_lock __attribute__ ((section("tzfw_coherent_mem")));
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#define LOCK_ARG &mhu_secure_lock
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#else
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#define LOCK_ARG JUNO_MHU_BAKERY_ID
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#endif /*__USE_COHERENT_MEM__ */
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#else
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#define LOCK_ARG /* Locks required only for BL3-1 images */
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#endif /* __IMAGE_BL31__ */
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void mhu_secure_message_start(void)
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{
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juno_lock_get(LOCK_ARG);
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/* Make sure any previous command has finished */
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while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) != 0)
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;
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}
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void mhu_secure_message_send(uint32_t command)
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{
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/* Send command to SCP and wait for it to pick it up */
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mmio_write_32(MHU_BASE + CPU_INTR_S_SET, command);
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while (mmio_read_32(MHU_BASE + CPU_INTR_S_STAT) != 0)
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;
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}
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uint32_t mhu_secure_message_wait(void)
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{
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/* Wait for response from SCP */
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uint32_t response;
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while (!(response = mmio_read_32(MHU_BASE + SCP_INTR_S_STAT)))
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;
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return response;
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}
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void mhu_secure_message_end(void)
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{
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/* Clear any response we got by writing all ones to the CLEAR register */
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mmio_write_32(MHU_BASE + SCP_INTR_S_CLEAR, 0xffffffffu);
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juno_lock_release(LOCK_ARG);
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}
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void mhu_secure_init(void)
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{
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juno_lock_init(LOCK_ARG);
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/*
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* Clear the CPU's INTR register to make sure we don't see a stale
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* or garbage value and think it's a message we've already sent.
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*/
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mmio_write_32(MHU_BASE + CPU_INTR_S_CLEAR, 0xffffffffu);
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}
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