mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2026-07-02 03:22:38 +00:00
Boyan Karatotev
270d5c5cd9
The FVP_Base models are all identical. Individual components can be swapped out without affecting the rest of the system. In order to not diverge too much, factor as much common stuff out but leave out interrupt information so that it can be swapped out. Change-Id: I4ce5b627c7ca00d98f10eba888cc1bf4d61880a9 Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
163 lines
3.3 KiB
Devicetree
163 lines
3.3 KiB
Devicetree
// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause
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/*
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* ARM Ltd. Fast Models
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*
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* Architecture Envelope Model (AEM) ARMv8-A
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* ARMAEMv8AMPCT
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*
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* RTSM_VE_AEMv8A.lisa
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*
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* Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved.
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*/
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#include "rtsm_ve-motherboard.dtsi"
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/ {
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model = "FVP Base";
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compatible = "arm,fvp-base", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs = "console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on";
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};
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2";
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method = "smc";
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max-pwr-lvl = <2>;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU_MAP
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idle-states {
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entry-method = "psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <40>;
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exit-latency-us = <100>;
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min-residency-us = <150>;
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <500>;
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exit-latency-us = <1000>;
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min-residency-us = <2500>;
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};
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};
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CPUS
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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memory@80000000 {
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device_type = "memory";
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#if (ENABLE_RME == 1)
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reg = <0x00000000 0x80000000 0 0x7C000000>,
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<0x00000008 0x80000000 0 0x80000000>;
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#else
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reg = <0x00000000 0x80000000 0 0x7F000000>,
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<0x00000008 0x80000000 0 0x80000000>;
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#endif
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* Chipselect 2,00000000 is physically at 0x18000000 */
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vram: vram@18000000 {
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/* 8 MB of designated video RAM */
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compatible = "shared-dma-pool";
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reg = <0x00000000 0x18000000 0 0x00800000>;
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no-map;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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clock-frequency = <100000000>;
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};
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timer@2a810000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x2a810000 0x0 0x10000>;
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clock-frequency = <100000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x2a810000 0x100000>;
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frame@2a830000 {
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frame-number = <1>;
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interrupt-parent = <&gic>;
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reg = <0x20000 0x10000>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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};
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panel {
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compatible = "arm,rtsm-display";
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port {
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panel_in: endpoint {
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remote-endpoint = <&clcd_pads>;
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};
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};
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};
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bus@8000000 {
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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};
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#if (ENABLE_RME == 1)
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pci: pci@40000000 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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compatible = "pci-host-ecam-generic";
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device_type = "pci";
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reg = <0x0 0x40000000 0x0 0x10000000>;
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ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>,
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/* First 3GB of 256GB PCIe memory region 2 */
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<0x2000000 0x40 0x00000000 0x40 0x00000000 0x0 0xc0000000>;
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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iommu-map = <0x0 &smmu 0x0 0x10000>;
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dma-coherent;
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};
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smmu: iommu@2b400000 {
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compatible = "arm,smmu-v3";
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reg = <0x0 0x2b400000 0x0 0x100000>;
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interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
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dma-coherent;
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#iommu-cells = <1>;
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};
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#endif /* ENABLE_RME */
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};
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