arm-trusted-firmware

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Bipin RaviandVarun Wadekar 330095fa4a fix(cpus): workaround for Cortex-A78C erratum 1827440

Cortex-A78C erratum 1827440 is a Cat B erratum that applies to
revision r0p0 and is fixed in r0p1.

The workaround is to set CPUACTLR2_EL1[2], which forces atomic store
operations to write-back memory to be performed in the L1 data cache.

SDEN documentation:
https://developer.arm.com/documentation/SDEN1707916/latest

Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I41d8ef48f70216ec66bf2b0f4f03ea8d8c261ee7
(cherry picked from commit b01a59eb2a)

2023-04-11 14:21:59 +01:00

alt-boot-flows.rst

doc: Split the User Guide into multiple files

2019-11-27 10:45:54 +00:00

auth-framework.rst

Cleanup the code for TBBR CoT descriptors

2020-05-19 05:05:19 +01:00

cpu-specific-build-macros.rst

fix(cpus): workaround for Cortex-A78C erratum 1827440

2023-04-11 14:21:59 +01:00

firmware-design.rst

feat: pass SMCCCv1.3 SVE hint bit to dispatchers