Govindraj RajaandVarun Wadekar 8c6068fab4 fix(cpus): workaround for accessing ICH_VMCR_EL2 ...

When ICH_VMCR_EL2.VBPR1 is written in Secure state (SCR_EL3.NS==0)
and then subsequently read in Non-secure state (SCR_EL3.NS==1), a
wrong value might be returned. The same issue exists in the opposite way.

Adding workaround in EL3 software that performs context save/restore
on a change of Security state to use a value of SCR_EL3.NS when
accessing ICH_VMCR_EL2 that reflects the Security state that owns the
data being saved or restored. For example, EL3 software should set
SCR_EL3.NS to 1 when saving or restoring the value ICH_VMCR_EL2 for
Non-secure(or Realm) state. EL3 software should clear
SCR_EL3.NS to 0 when saving or restoring the value ICH_VMCR_EL2 for
Secure state.

SDEN documentation:
https://developer.arm.com/documentation/SDEN-1775101/latest/

Change-Id: I9f0403601c6346276e925f02eab55908b009d957
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
(cherry picked from commit 7455cd1721)

2025-02-18 13:01:42 +00:00

..

aarch32

refactor(context mgmt): add cm_prepare_el3_exit_ns function

2022-04-12 17:42:11 +02:00

aarch64

fix(cpus): workaround for accessing ICH_VMCR_EL2

2025-02-18 13:01:42 +00:00

cpu_data_array.c

Sanitise includes across codebase

2019-01-04 10:43:17 +00:00