Maninder SinghandVarun Wadekar 1414e0adda fix(nxp-ddr): apply Max CDD values for warm boot ...

Timing CFG 0 and Timing CFG 4 are ddr controller registers that
have been affected by 1d phy training during cold boot. They are
needed to be stored and restored along with phy training values.

Signed-off-by: Maninder Singh <maninder.singh_1@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I29c55256e74456515aaeb098e2e0e3475697a466
(cherry picked from commit 00bb8c37e0)

2023-02-03 17:06:51 +00:00

..

fsl-mmdc

refactor: moved drivers hdr files to include/drivers/nxp

2021-08-03 12:19:56 +02:00

nxp-ddr

feat(nxp-ddr): add workaround for errata A050958

2022-03-27 23:24:24 +08:00

phy-gen1

nxp: ddr driver enablement for nxp layerscape soc

2021-03-24 09:49:31 +05:30

phy-gen2

fix(nxp-ddr): apply Max CDD values for warm boot

2023-02-03 17:06:51 +00:00