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https://github.com/ARM-software/arm-trusted-firmware.git
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Wilson DingandWilson Ding
6d5fad8d9e
Armada-7K/8K and CN913x integrated the Rambus EIP-97 IP on CP11x die. It supports to generate up to 4 32-bit random number in one shot. This trivial driver provisions a simple API to read the random numbers from hardware. It allows the bootloader to get one 32-bit or 64-bit random number via SMC call to support KASLR. Change-Id: I1707a85512ca163b8c7ab1644ff0f7e2fcf57344 Signed-off-by: Wilson Ding <dingwei@marvell.com>
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/*
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* Copyright (c) 2025, Marvell Technology Group Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/delay_timer.h>
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#include <lib/mmio.h>
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#include <mvebu_def.h>
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/* Bind to first CP110's EIP-76 engine only */
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#define CP110_TRNG_REGS_BASE (MVEBU_CP_REGS_BASE(0) + 0x760000U)
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/* EIP-76 Register Definitions */
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#define CP110_TRNG_OUTPUT_REG(n) (CP110_TRNG_REGS_BASE + ((n) * 0x4U))
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#define CP110_TRNG_STAT_N_ACK_REG (CP110_TRNG_REGS_BASE + 0x10U)
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#define CP110_TRNG_CONTROL_REG (CP110_TRNG_REGS_BASE + 0x14U)
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#define CP110_TRNG_CONFIG_REG (CP110_TRNG_REGS_BASE + 0x18U)
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#define CP110_TRNG_FRO_ENABLE_REG (CP110_TRNG_REGS_BASE + 0x20U)
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#define CP110_TRNG_FRO_DETUNE_REG (CP110_TRNG_REGS_BASE + 0x24U)
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/* CP110_TRNG_STAT_N_ACK_REG */
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#define CP110_TRNG_READY BIT(0)
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/* CP110_TRNG_CONTROL_REG */
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#define CP110_TRNG_EN BIT(10)
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/* CP110_TRNG_CONFIG_REG */
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#define CP110_TRNG_NOISE_BLOCKS_SHIFT 0U
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#define CP110_TRNG_NOISE_BLOCKS_MASK (0xFFU << CP110_TRNG_NOISE_BLOCKS_SHIFT)
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#define CP110_TRNG_SAMPLE_CYCLES_SHIFT 16U
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#define CP110_TRNG_SAMPLE_CYCLES_MASK (0xFFU << CP110_TRNG_SAMPLE_CYCLES_SHIFT)
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/* CP110_TRNG_FRO_ENABLE_REG */
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#define CP110_TRNG_FRO_EN_SHIFT 0U
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#define CP110_TRNG_FRO_EN_MASK (0xFFFFFFU << CP110_TRNG_FRO_EN_SHIFT)
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#define CP110_TRNG_MAX_OUTPUTS 4U
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/* maximum busy wait */
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#define CP110_TRNG_MAX_RETRIES 3U
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static void mv_trng_init(void)
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{
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uint32_t val;
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val = (0x5U << CP110_TRNG_NOISE_BLOCKS_SHIFT) & CP110_TRNG_NOISE_BLOCKS_MASK;
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val |= (0x22U << CP110_TRNG_SAMPLE_CYCLES_SHIFT) & CP110_TRNG_SAMPLE_CYCLES_MASK;
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mmio_write_32(CP110_TRNG_CONFIG_REG, val);
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mmio_write_32(CP110_TRNG_FRO_DETUNE_REG, 0U);
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mmio_write_32(CP110_TRNG_FRO_ENABLE_REG, CP110_TRNG_FRO_EN_MASK);
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mmio_write_32(CP110_TRNG_CONTROL_REG, CP110_TRNG_EN);
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}
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int mv_trng_get_random32(uint32_t *rand, uint8_t num)
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{
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uint32_t val;
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uint8_t i;
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if (num > CP110_TRNG_MAX_OUTPUTS) {
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return -1;
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}
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val = mmio_read_32(CP110_TRNG_CONTROL_REG);
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if ((val & CP110_TRNG_EN) != 0U) {
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/* Flush the staled output data */
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val = mmio_read_32(CP110_TRNG_STAT_N_ACK_REG);
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if ((val & CP110_TRNG_READY) != 0U) {
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mmio_write_32(CP110_TRNG_STAT_N_ACK_REG, CP110_TRNG_READY);
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}
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} else {
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mv_trng_init();
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/* Necessary delay for the warm-up */
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udelay(200U);
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}
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for (i = 0U; i < CP110_TRNG_MAX_RETRIES; i++) {
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val = mmio_read_32(CP110_TRNG_STAT_N_ACK_REG);
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if ((val & CP110_TRNG_READY) != 0U) {
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break;
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}
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udelay(1U);
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}
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if (i == CP110_TRNG_MAX_RETRIES) {
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return -1;
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}
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for (i = 0U; i < num; i++) {
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rand[i] = mmio_read_32(CP110_TRNG_OUTPUT_REG(i));
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}
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return 0;
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}
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