mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2026-07-05 01:18:49 +00:00
John PowellandGovindraj Raja
1fcfcad3bb
This workaround fixes an issue with the CPP RCTX instruction by
issuing an instruction patch sequence to trap uses of the CPP RCTX
instruction from EL0, EL1, and EL2 to EL3 and perform a workaround
procedure using the implementation defined trap handler to ensure
the correct behavior of the system. In addition, it includes an EL3
API to be used if EL3 firmware needs to use the CPP RCTX instruction.
This saves the overhead of exception handling, and EL3 does not
generically support trapping EL3->EL3, and adding support for that
is not trivial due to the implications for context management.
The issue affects the following CPUs:
C1-Premium
C1-Ultra
Cortex-A710
Cortex-X2
Cortex-X3
Cortex-X4
Cortex-X925
Neoverse N2
Neoverse V2
Neoverse V3
Neoverse V3AE (handled same as V3 CPU in TF-A CPU-Lib)
Arm Security Bulletin Document:
https://developer.arm.com/documentation/111546
Change-Id: I5e7589afbeb69ebb79c01bec80e29f572aff3d89
Signed-off-by: John Powell <john.powell@arm.com>
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
(cherry picked from commit 416b8613bc)
442 lines
14 KiB
Makefile
442 lines
14 KiB
Makefile
#
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# Copyright (c) 2025-2026, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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ifneq ($(AARCH32_INSTRUCTION_SET),$(filter $(AARCH32_INSTRUCTION_SET),A32 T32))
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$(error Error: Unknown AArch32 instruction set ${AARCH32_INSTRUCTION_SET})
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endif
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# Make sure RME configuration is valid
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ifeq (${ENABLE_RME},1)
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ifneq (${SEPARATE_CODE_AND_RODATA},1)
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$(error ENABLE_RME requires SEPARATE_CODE_AND_RODATA)
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endif
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ifneq (${ARCH},aarch64)
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$(error ENABLE_RME requires AArch64)
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endif
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ifeq ($(SPMC_AT_EL3),1)
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$(error SPMC_AT_EL3 and ENABLE_RME cannot both be enabled.)
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endif
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ifneq (${SPD}, none)
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ifneq (${SPD}, spmd)
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$(error ENABLE_RME is incompatible with SPD=${SPD}. Use SPD=spmd)
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endif
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endif
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else
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ifeq (${ENABLE_FEAT_RME_GDI},1)
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$(error ENABLE_FEAT_RME_GDI requires ENABLE_RME)
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endif
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endif
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ifeq (${CTX_INCLUDE_EL2_REGS}, 1)
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ifeq (${SPD},none)
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ifeq (${ENABLE_RME},0)
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$(error CTX_INCLUDE_EL2_REGS is available only when SPD \
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or RME is enabled)
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endif
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endif
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endif
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################################################################################
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# Verify FEAT_RME, FEAT_SCTLR2 and FEAT_TCR2 are enabled if FEAT_MEC is enabled.
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################################################################################
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ifneq (${ENABLE_FEAT_MEC},0)
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ifeq (${ENABLE_RME},0)
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$(error FEAT_RME must be enabled when FEAT_MEC is enabled.)
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endif
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ifeq (${ENABLE_FEAT_TCR2},0)
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$(error FEAT_TCR2 must be enabled when FEAT_MEC is enabled.)
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endif
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ifeq (${ENABLE_FEAT_SCTLR2},0)
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$(error FEAT_SCTLR2 must be enabled when FEAT_MEC is enabled.)
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endif
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endif
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# Handle all invalid build configurations with SPMD usage.
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ifeq (${ENABLE_SPMD_LP}, 1)
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ifneq (${SPD},spmd)
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$(error Error: ENABLE_SPMD_LP requires SPD=spmd.)
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endif
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ifeq ($(SPMC_AT_EL3),1)
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$(error SPMC at EL3 not supported when enabling SPMD Logical partitions.)
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endif
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endif
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ifneq (${SPD},none)
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ifeq (${ARCH},aarch32)
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$(error "Error: SPD is incompatible with AArch32.")
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endif
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ifdef EL3_PAYLOAD_BASE
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$(warning "SPD and EL3_PAYLOAD_BASE are incompatible build options.")
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$(warning "The SPD and its BL32 companion will be present but ignored.")
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endif
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ifeq (${SPD},spmd)
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ifeq ($(SPMD_SPM_AT_SEL2),1)
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ifeq ($(SPMC_AT_EL3),1)
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$(error SPM cannot be enabled in both S-EL2 and EL3.)
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endif
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ifeq ($(CTX_INCLUDE_SVE_REGS),1)
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$(error SVE context management not needed with Hafnium SPMC.)
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endif
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endif
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ifeq ($(SPMC_AT_EL3_SEL0_SP),1)
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ifneq ($(SPMC_AT_EL3),1)
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$(error SEL0 SP cannot be enabled without SPMC at EL3)
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endif
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endif
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endif #(SPD=spmd)
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endif #(SPD!=none)
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# USE_DEBUGFS experimental feature recommended only in debug builds
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ifeq (${USE_DEBUGFS},1)
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ifeq (${DEBUG},1)
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$(warning DEBUGFS experimental feature is enabled.)
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else
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$(warning DEBUGFS experimental, recommended in DEBUG builds ONLY)
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endif
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endif #(USE_DEBUGFS)
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# USE_SPINLOCK_CAS requires AArch64 build
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ifeq (${USE_SPINLOCK_CAS},1)
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ifneq (${ARCH},aarch64)
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$(error USE_SPINLOCK_CAS requires AArch64)
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endif
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endif #(USE_SPINLOCK_CAS)
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ifdef EL3_PAYLOAD_BASE
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ifdef PRELOADED_BL33_BASE
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$(warning "PRELOADED_BL33_BASE and EL3_PAYLOAD_BASE are \
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incompatible build options. EL3_PAYLOAD_BASE has priority.")
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endif
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ifneq (${GENERATE_COT},0)
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$(error "GENERATE_COT and EL3_PAYLOAD_BASE are incompatible \
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build options.")
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endif
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ifneq (${TRUSTED_BOARD_BOOT},0)
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$(error "TRUSTED_BOARD_BOOT and EL3_PAYLOAD_BASE are \
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incompatible \ build options.")
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endif
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endif #(EL3_PAYLOAD_BASE)
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ifeq (${NEED_BL33},yes)
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ifdef EL3_PAYLOAD_BASE
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$(warning "BL33 image is not needed when option \
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BL33_PAYLOAD_BASE is used and won't be added to the FIP file.")
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endif
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ifdef PRELOADED_BL33_BASE
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$(warning "BL33 image is not needed when option \
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PRELOADED_BL33_BASE is used and won't be added to the FIP file.")
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endif
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endif #(NEED_BL33)
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# When building for systems with hardware-assisted coherency, there's no need to
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# use USE_COHERENT_MEM. Require that USE_COHERENT_MEM must be set to 0 too.
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ifeq ($(HW_ASSISTED_COHERENCY)-$(USE_COHERENT_MEM),1-1)
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$(error USE_COHERENT_MEM cannot be enabled with HW_ASSISTED_COHERENCY)
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endif
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#For now, BL2_IN_XIP_MEM is only supported when RESET_TO_BL2 is 1.
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ifeq ($(RESET_TO_BL2)-$(BL2_IN_XIP_MEM),0-1)
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$(error "BL2_IN_XIP_MEM is only supported when RESET_TO_BL2 is enabled")
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endif
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# RAS_EXTENSION is deprecated, provide alternate build options
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ifeq ($(RAS_EXTENSION),1)
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$(error "RAS_EXTENSION is now deprecated, please use ENABLE_FEAT_RAS \
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and HANDLE_EA_EL3_FIRST_NS instead")
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endif
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# When FAULT_INJECTION_SUPPORT is used, require that FEAT_RAS is enabled
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ifeq ($(FAULT_INJECTION_SUPPORT),1)
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ifeq ($(ENABLE_FEAT_RAS),0)
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$(error For FAULT_INJECTION_SUPPORT, ENABLE_FEAT_RAS must not be 0)
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endif
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endif #(FAULT_INJECTION_SUPPORT)
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# DYN_DISABLE_AUTH can be set only when TRUSTED_BOARD_BOOT=1
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ifeq ($(DYN_DISABLE_AUTH), 1)
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ifeq (${TRUSTED_BOARD_BOOT}, 0)
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$(error "TRUSTED_BOARD_BOOT must be enabled for DYN_DISABLE_AUTH \
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to be set.")
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endif
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endif #(DYN_DISABLE_AUTH)
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# SDEI_IN_FCONF is only supported when SDEI_SUPPORT is enabled.
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ifeq ($(SDEI_SUPPORT)-$(SDEI_IN_FCONF),0-1)
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$(error "SDEI_IN_FCONF is only supported when SDEI_SUPPORT is enabled")
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endif
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# If pointer authentication is used in the firmware, make sure that all the
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# registers associated to it are also saved and restored.
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# Not doing it would leak the value of the keys used by EL3 to EL1 and S-EL1.
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ifneq ($(ENABLE_PAUTH),0)
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ifeq ($(CTX_INCLUDE_PAUTH_REGS),0)
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$(error Pointer Authentication requires CTX_INCLUDE_PAUTH_REGS to be enabled)
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endif
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endif #(ENABLE_PAUTH)
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ifneq ($(CTX_INCLUDE_PAUTH_REGS),0)
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ifneq (${ARCH},aarch64)
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$(error CTX_INCLUDE_PAUTH_REGS requires AArch64)
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endif
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endif #(CTX_INCLUDE_PAUTH_REGS)
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# Check ENABLE_FEAT_PAUTH_LR
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ifneq (${ENABLE_FEAT_PAUTH_LR},0)
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# Make sure PAUTH is enabled
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ifeq (${ENABLE_PAUTH},0)
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$(error Error: PAUTH_LR cannot be used without PAUTH (see BRANCH_PROTECTION))
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endif
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# Make sure SCTLR2 is enabled
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ifeq (${ENABLE_FEAT_SCTLR2},0)
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$(error Error: PAUTH_LR cannot be used without ENABLE_FEAT_SCTLR2)
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endif
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# FEAT_PAUTH_LR is only supported in aarch64 state
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ifneq (${ARCH},aarch64)
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$(error ENABLE_FEAT_PAUTH_LR requires AArch64)
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endif
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endif # ${ENABLE_FEAT_PAUTH_LR}
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ifeq ($(FEATURE_DETECTION),1)
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$(info FEATURE_DETECTION is an experimental feature)
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endif #(FEATURE_DETECTION)
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ifneq ($(ENABLE_SME2_FOR_NS), 0)
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ifeq (${ENABLE_SME_FOR_NS}, 0)
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$(warning "ENABLE_SME2_FOR_NS requires ENABLE_SME_FOR_NS also \
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to be set")
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$(warning "Forced ENABLE_SME_FOR_NS=1")
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override ENABLE_SME_FOR_NS := 1
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endif
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endif #(ENABLE_SME2_FOR_NS)
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ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
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ifeq (${ALLOW_RO_XLAT_TABLES}, 1)
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$(error "ALLOW_RO_XLAT_TABLES requires translation tables \
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library v2")
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endif
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endif #(ARM_XLAT_TABLES_LIB_V1)
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ifneq (${DECRYPTION_SUPPORT},none)
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ifeq (${TRUSTED_BOARD_BOOT}, 0)
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$(error TRUSTED_BOARD_BOOT must be enabled for DECRYPTION_SUPPORT \
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to be set)
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endif
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endif #(DECRYPTION_SUPPORT)
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# Ensure that no Aarch64-only features are enabled in Aarch32 build
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ifeq (${ARCH},aarch32)
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ifneq (${ENABLE_LTO},0)
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$(error "ENABLE_LTO is not supported with ARCH=aarch32")
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endif
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ifneq (${EL3_EXCEPTION_HANDLING},0)
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$(error "EL3_EXCEPTION_HANDLING is not supported outside BL31")
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endif
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ifeq (${CRASH_REPORTING},1)
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$(error "CRASH_REPORTING is not supported with ARCH=aarch32")
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endif
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# SME/SVE only supported on AArch64
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ifneq (${ENABLE_SME_FOR_NS},0)
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$(error "ENABLE_SME_FOR_NS cannot be used with ARCH=aarch32")
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endif
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ifeq (${ENABLE_SVE_FOR_NS},1)
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# Warning instead of error due to CI dependency on this
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$(error "ENABLE_SVE_FOR_NS cannot be used with ARCH=aarch32")
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endif
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# BRBE is not supported in AArch32
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ifeq (${ENABLE_BRBE_FOR_NS},1)
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$(error "ENABLE_BRBE_FOR_NS cannot be used with ARCH=aarch32")
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endif
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# FEAT_RNG_TRAP is not supported in AArch32
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ifneq (${ENABLE_FEAT_RNG_TRAP},0)
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$(error "ENABLE_FEAT_RNG_TRAP cannot be used with ARCH=aarch32")
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endif
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ifneq (${ENABLE_FEAT_FPMR},0)
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$(error "ENABLE_FEAT_FPMR cannot be used with ARCH=aarch32")
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endif
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ifeq (${ARCH_FEATURE_AVAILABILITY},1)
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$(error "ARCH_FEATURE_AVAILABILITY cannot be used with ARCH=aarch32")
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endif
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# FEAT_MOPS is only supported on AArch64
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ifneq (${ENABLE_FEAT_MOPS},0)
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$(error "ENABLE_FEAT_MOPS cannot be used with ARCH=aarch32")
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endif
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ifneq (${ENABLE_FEAT_GCIE},0)
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$(error "ENABLE_FEAT_GCIE cannot be used with ARCH=aarch32")
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endif
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ifneq (${ENABLE_FEAT_CPA2},0)
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$(error "ENABLE_FEAT_CPA2 cannot be used with ARCH=aarch32")
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endif
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ifneq (${PLATFORM_NODE_COUNT},1)
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$(error "NUMA AWARE PER CPU is not supported with ARCH=aarch32")
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endif
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endif #(ARCH=aarch32)
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ifneq (${ENABLE_FEAT_FPMR},0)
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ifeq (${ENABLE_FEAT_FGT},0)
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$(error "ENABLE_FEAT_FPMR requires ENABLE_FEAT_FGT")
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endif
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ifeq (${ENABLE_FEAT_HCX},0)
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$(error "ENABLE_FEAT_FPMR requires ENABLE_FEAT_HCX")
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endif
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endif #(ENABLE_FEAT_FPMR)
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ifneq (${ENABLE_FEAT_CPA2},0)
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ifeq (${ENABLE_FEAT_SCTLR2},0)
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$(error "Error: ENABLE_FEAT_CPA2 cannot be used without ENABLE_FEAT_SCTLR2")
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endif
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endif #${ENABLE_FEAT_CPA2}
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ifneq (${ENABLE_SME_FOR_NS},0)
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ifeq (${ENABLE_SVE_FOR_NS},0)
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$(error "ENABLE_SME_FOR_NS requires ENABLE_SVE_FOR_NS")
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endif
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endif #(ENABLE_SME_FOR_NS)
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# Secure SME/SVE requires the non-secure component as well
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ifeq (${ENABLE_SME_FOR_SWD},1)
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ifeq (${ENABLE_SME_FOR_NS},0)
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$(error "ENABLE_SME_FOR_SWD requires ENABLE_SME_FOR_NS")
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endif
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ifeq (${ENABLE_SVE_FOR_SWD},0)
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$(error "ENABLE_SME_FOR_SWD requires ENABLE_SVE_FOR_SWD")
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endif
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endif #(ENABLE_SME_FOR_SWD)
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# Enabling SVE for SWD requires enabling SVE for NWD due to ENABLE_FEAT
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# mechanism.
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ifeq (${ENABLE_SVE_FOR_SWD},1)
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ifeq (${ENABLE_SVE_FOR_NS},0)
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$(error "ENABLE_SVE_FOR_SWD requires ENABLE_SVE_FOR_NS")
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endif
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endif
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# Enabling FEAT_MOPS requires access to hcrx_el2 registers which is
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# available only when FEAT_HCX is enabled.
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ifneq (${ENABLE_FEAT_MOPS},0)
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ifeq (${ENABLE_FEAT_HCX},0)
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$(error "ENABLE_FEAT_MOPS requires ENABLE_FEAT_HCX")
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endif
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endif
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# Enabling SVE for both the worlds typically requires the context
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# management of SVE registers. The only exception being SPMC at S-EL2.
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ifeq (${ENABLE_SVE_FOR_SWD}, 1)
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ifneq (${ENABLE_SVE_FOR_NS}, 0)
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ifeq (${CTX_INCLUDE_SVE_REGS}-$(SPMD_SPM_AT_SEL2),0-0)
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$(warning "ENABLE_SVE_FOR_SWD and ENABLE_SVE_FOR_NS together require CTX_INCLUDE_SVE_REGS")
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endif
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endif
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endif
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# Enabling SVE in either world while enabling CTX_INCLUDE_FPREGS requires
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# CTX_INCLUDE_SVE_REGS to be enabled due to architectural dependency between FP
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# and SVE registers.
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ifeq (${CTX_INCLUDE_FPREGS}, 1)
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ifneq (${ENABLE_SVE_FOR_NS},0)
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ifeq (${CTX_INCLUDE_SVE_REGS},0)
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# Warning instead of error due to CI dependency on this
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$(warning "CTX_INCLUDE_FPREGS and ENABLE_SVE_FOR_NS together require CTX_INCLUDE_SVE_REGS")
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$(warning "Forced ENABLE_SVE_FOR_NS=0")
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override ENABLE_SVE_FOR_NS := 0
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endif
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endif
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endif #(CTX_INCLUDE_FPREGS)
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# SVE context management is only required if secure world has access to SVE/FP
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# functionality.
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# Enabling CTX_INCLUDE_SVE_REGS requires CTX_INCLUDE_FPREGS to be enabled due
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# to architectural dependency between FP and SVE registers.
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ifeq (${CTX_INCLUDE_SVE_REGS},1)
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ifeq (${ENABLE_SVE_FOR_SWD},0)
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$(error "CTX_INCLUDE_SVE_REGS requires ENABLE_SVE_FOR_SWD to also be enabled")
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endif
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ifeq (${CTX_INCLUDE_FPREGS},0)
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$(error "CTX_INCLUDE_SVE_REGS requires CTX_INCLUDE_FPREGS to also be enabled")
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endif #(CTX_INCLUDE_FPREGS)
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endif #(CTX_INCLUDE_SVE_REGS)
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# SME cannot be used with CTX_INCLUDE_FPREGS since SPM does its own context
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# management including FPU registers.
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ifeq (${CTX_INCLUDE_FPREGS},1)
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ifneq (${ENABLE_SME_FOR_NS},0)
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$(error "ENABLE_SME_FOR_NS cannot be used with CTX_INCLUDE_FPREGS")
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endif
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endif #(CTX_INCLUDE_FPREGS)
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ifeq ($(DRTM_SUPPORT),1)
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$(info DRTM_SUPPORT is an experimental feature)
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endif
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ifeq (${HOB_LIST},1)
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$(warning HOB_LIST is an experimental feature)
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endif
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ifeq (${TRANSFER_LIST},1)
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$(info TRANSFER_LIST is an experimental feature)
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endif
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ifeq ($(PSA_CRYPTO),1)
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$(info PSA_CRYPTO is an experimental feature)
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endif
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ifeq ($(DICE_PROTECTION_ENVIRONMENT),1)
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$(info DICE_PROTECTION_ENVIRONMENT is an experimental feature)
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endif
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ifeq (${LFA_SUPPORT},1)
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$(warning LFA_SUPPORT is an experimental feature)
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endif #(LFA_SUPPORT)
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ifneq (${ENABLE_FEAT_MPAM_PE_BW_CTRL},0)
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ifeq (${ENABLE_FEAT_MPAM},0)
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$(error "ENABLE_FEAT_MPAM_PW_BW_CTRL requires ENABLE_FEAT_MPAM")
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endif
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endif #(ENABLE_FEAT_MPAM_PE_BW_CTRL)
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ifneq (${DYNAMIC_WORKAROUND_CVE_2018_3639},0)
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ifeq (${WORKAROUND_CVE_2018_3639},0)
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$(error Error: WORKAROUND_CVE_2018_3639 must be 1 if DYNAMIC_WORKAROUND_CVE_2018_3639 is 1)
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endif
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endif
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ifeq (${WORKAROUND_CVE_2025_0647},1)
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ifeq "8.5" "$(word 1, $(sort 8.5 $(ARM_ARCH_MAJOR).$(ARM_ARCH_MINOR)))"
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else
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$(error Error: WORKAROUND_CVE_2025_0647 can only be used with Arm Arch v8.5+, set ARM_ARCH_MAJOR and ARM_ARCH_MINOR appropriately.)
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endif
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endif
|
|
|
|
# Handle all deprecated build options.
|
|
ifeq (${ERROR_DEPRECATED}, 1)
|
|
ifneq (${NS_TIMER_SWITCH},0)
|
|
$(error "NS_TIMER_SWITCH breaks Linux preemption model, hence deprecated")
|
|
endif
|
|
ifneq (${SPM_MM},0)
|
|
$(error "SPM_MM build option is deprecated")
|
|
endif
|
|
endif
|
|
|
|
ifneq (${ENABLE_FEAT_IDTE3},0)
|
|
$(info FEAT_IDTE3 is an experimental feature)
|
|
endif #(ENABLE_FEAT_IDTE3)
|