Arvind Ram Prakash c42aefd3eb feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support ...

Implement support for FEAT_MPAM_PE_BW_CTRL, allowing lower
Exception Levels to access MPAM_PE_BW_CTRL control registers
by disabling their traps to EL3.

When INIT_UNUSED_NS_EL2=1, configure MPAMBW2_EL2 in EL3 so
that MPAM_PE_BW_CTRL accesses from EL0/EL1 do not trap to EL2.

At this stage, PE-side MPAM bandwidth controls remain disabled
in EL3.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I8e359b0eb912cff3bdda109b21727a627cac3a7e

2025-08-28 10:39:52 -05:00

..

mpam.c

feat(cpufeat): enable FEAT_MPAM_PE_BW_CTRL support

2025-08-28 10:39:52 -05:00