mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2026-07-01 16:54:47 +00:00
Boyan KaratotevandGovindraj Raja
0b29e2c4fc
It is possible for the cpu_data structure to be cached somewhere in the
cache hierarchy. When HW_ASSISTED_COHERENCY == 0 we flush the core's
private caches (usually the L1). However, the destination might be
shared caches (eg DSU L2 cache) so when we subsequently dereference the
cpu_data pointer we could get a stale value.
So dereference it prior to disabling the caches to avoid this scenario
and do all accesses from a coherent view of memory.
Change-Id: If118ca8c0436dd04d6ad0d57073d69305a7f41cb
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
(cherry picked from commit 0ee188d055)