mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2026-07-04 18:18:43 +00:00
Amr MohamedandAhmed Azeem
b666f0a1a9
Adjust the platform's CPU topology in the device tree file based on the passed build time topology. If no build time topology was provided, default topology will be used. Change-Id: Ied48f27f32d8f7a7df138a98075848c59f7435c0 Signed-off-by: Amr Mohamed <amr.mohamed@arm.com>
354 lines
8.2 KiB
Devicetree
354 lines
8.2 KiB
Devicetree
/*
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* Copyright (c) 2025, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RDASPEN_DEFS_DTSI
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#define RDASPEN_DEFS_DTSI
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#include <platform_def.h>
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#define CPU(cluster_num, cluster_core_num, cpu_num, mpid) \
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CPU##cpu_num:cpu@mpid## { \
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device_type = "cpu"; \
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compatible = "arm,cortex-a720ae"; \
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reg = <0x0 0x##mpid>; \
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enable-method = "psci"; \
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i-cache-size = <0x10000>; \
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i-cache-line-size = <0x40>; \
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i-cache-sets = <0x100>; \
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d-cache-size = <0x10000>; \
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d-cache-line-size = <0x40>; \
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d-cache-sets = <0x100>; \
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next-level-cache = <&CL##cluster_num##_L2_##cluster_core_num>; \
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CL##cluster_num##_L2_##cluster_core_num: l2-cache##cpu_num { \
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compatible = "cache"; \
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cache-unified; \
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cache-level = <0x02>; \
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/* 512KB */ \
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cache-size = <0x80000>; \
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/* 64B */ \
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cache-line-size = <0x40>; \
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/* 8-way set */ \
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cache-sets = <0x400>; \
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next-level-cache = <&CL##cluster_num##_L3>; \
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}; \
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};
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#define CORE(cluster_core_num, cpu_num) \
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core##cluster_core_num { \
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cpu = <&CPU##cpu_num>; \
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};
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#define CLUSTER_L3_CACHE(cluster_num) \
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CL##cluster_num##_L3: l3-cache##cluster_num## { \
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compatible = "arm,dsu-l3-cache", "cache"; \
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cache-level = <0x03>; \
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/* 4MB */ \
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cache-size = <0x400000>; \
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/* 64B */ \
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cache-line-size = <0x40>; \
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/* 16-way set */ \
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cache-sets = <0x1000>; \
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};
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#define CLUSTER_DSU_PMU(cluster_num, cpu_list, interrupt_map) \
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dsu-pmu-##cluster_num { \
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compatible = "arm,dsu-pmu"; \
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cpus = ##cpu_list; \
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interrupts = ##interrupt_map; \
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};
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#define CLUSTER_0_DSU_PMU_INTERRUPT_MAP <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>
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#define CLUSTER_1_DSU_PMU_INTERRUPT_MAP <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>
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#define CLUSTER_2_DSU_PMU_INTERRUPT_MAP <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>
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#define CLUSTER_3_DSU_PMU_INTERRUPT_MAP <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>
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#if (PLATFORM_CLUSTER_0_CORE_COUNT == 1)
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#define CLUSTER_0_CPU_LIST \
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CORE(0, 0)
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#define CLUSTER_0_CPUS \
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CPU(0, 0, 0, 0)
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#define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>
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#elif (PLATFORM_CLUSTER_0_CORE_COUNT == 2)
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#define CLUSTER_0_CPU_LIST \
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CORE(0, 0) \
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CORE(1, 1)
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#define CLUSTER_0_CPUS \
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CPU(0, 0, 0, 0) \
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CPU(0, 1, 1, 100)
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#define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1>
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#elif (PLATFORM_CLUSTER_0_CORE_COUNT == 3)
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#define CLUSTER_0_CPU_LIST \
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CORE(0, 0) \
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CORE(1, 1) \
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CORE(2, 2)
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#define CLUSTER_0_CPUS \
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CPU(0, 0, 0, 0) \
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CPU(0, 1, 1, 100) \
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CPU(0, 2, 2, 200)
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#define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1>, <&CPU2>
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#elif (PLATFORM_CLUSTER_0_CORE_COUNT == 4)
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#define CLUSTER_0_CPU_LIST \
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CORE(0, 0) \
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CORE(1, 1) \
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CORE(2, 2) \
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CORE(3, 3)
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#define CLUSTER_0_CPUS \
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CPU(0, 0, 0, 0) \
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CPU(0, 1, 1, 100) \
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CPU(0, 2, 2, 200) \
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CPU(0, 3, 3, 300)
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#define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>
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#endif
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#if (PLATFORM_CLUSTER_1_CORE_COUNT == 1)
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#define CLUSTER_1_CPU_LIST \
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CORE(0, 4)
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#define CLUSTER_1_CPUS \
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CPU(1, 0, 4, 10000)
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#define CLUSTER_1_DSU_PMU_CPU_LIST <&CPU4>
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#elif (PLATFORM_CLUSTER_1_CORE_COUNT == 2)
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#define CLUSTER_1_CPU_LIST \
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CORE(0, 4) \
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CORE(1, 5)
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#define CLUSTER_1_CPUS \
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CPU(1, 0, 4, 10000) \
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CPU(1, 1, 5, 10100)
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#define CLUSTER_1_DSU_PMU_CPU_LIST <&CPU4>, <&CPU5>
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#elif (PLATFORM_CLUSTER_1_CORE_COUNT == 3)
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#define CLUSTER_1_CPU_LIST \
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CORE(0, 4) \
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CORE(1, 5) \
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CORE(2, 6)
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#define CLUSTER_1_CPUS \
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CPU(1, 0, 4, 10000) \
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CPU(1, 1, 5, 10100) \
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CPU(1, 2, 6, 10200)
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#define CLUSTER_1_DSU_PMU_CPU_LIST <&CPU4>, <&CPU5>, <&CPU6>
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#elif (PLATFORM_CLUSTER_1_CORE_COUNT == 4)
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#define CLUSTER_1_CPU_LIST \
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CORE(0, 4) \
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CORE(1, 5) \
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CORE(2, 6) \
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CORE(3, 7)
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#define CLUSTER_1_CPUS \
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CPU(1, 0, 4, 10000) \
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CPU(1, 1, 5, 10100) \
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CPU(1, 2, 6, 10200) \
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CPU(1, 3, 7, 10300)
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#define CLUSTER_1_DSU_PMU_CPU_LIST <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>
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#endif
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#if (PLATFORM_CLUSTER_2_CORE_COUNT == 1)
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#define CLUSTER_2_CPU_LIST \
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CORE(0, 8)
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#define CLUSTER_2_CPUS \
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CPU(2, 0, 8, 20000)
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#define CLUSTER_2_DSU_PMU_CPU_LIST <&CPU8>
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#elif (PLATFORM_CLUSTER_2_CORE_COUNT == 2)
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#define CLUSTER_2_CPU_LIST \
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CORE(0, 8) \
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CORE(1, 9)
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#define CLUSTER_2_CPUS \
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CPU(2, 0, 8, 20000) \
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CPU(2, 1, 9, 20100)
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#define CLUSTER_2_DSU_PMU_CPU_LIST <&CPU8>, <&CPU9>
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#elif (PLATFORM_CLUSTER_2_CORE_COUNT == 3)
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#define CLUSTER_2_CPU_LIST \
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CORE(0, 8) \
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CORE(1, 9) \
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CORE(2, 10)
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#define CLUSTER_2_CPUS \
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CPU(2, 0, 8, 20000) \
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CPU(2, 1, 9, 20100) \
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CPU(2, 2, 10, 20200)
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#define CLUSTER_2_DSU_PMU_CPU_LIST <&CPU8>, <&CPU9>, <&CPU10>
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#elif (PLATFORM_CLUSTER_2_CORE_COUNT == 4)
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#define CLUSTER_2_CPU_LIST \
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CORE(0, 8) \
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CORE(1, 9) \
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CORE(2, 10) \
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CORE(3, 11)
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#define CLUSTER_2_CPUS \
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CPU(2, 0, 8, 20000) \
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CPU(2, 1, 9, 20100) \
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CPU(2, 2, 10, 20200) \
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CPU(2, 3, 11, 20300)
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#define CLUSTER_2_DSU_PMU_CPU_LIST <&CPU8>, <&CPU9>, <&CPU10>, <&CPU11>
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#endif
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#if (PLATFORM_CLUSTER_3_CORE_COUNT == 1)
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#define CLUSTER_3_CPU_LIST \
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CORE(0, 12)
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#define CLUSTER_3_CPUS \
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CPU(3, 0, 12, 30000)
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#define CLUSTER_3_DSU_PMU_CPU_LIST <&CPU12>
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#elif (PLATFORM_CLUSTER_3_CORE_COUNT == 2)
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#define CLUSTER_3_CPU_LIST \
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CORE(0, 12) \
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CORE(1, 13)
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#define CLUSTER_3_CPUS \
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CPU(3, 0, 12, 30000) \
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CPU(3, 1, 13, 30100)
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#define CLUSTER_3_DSU_PMU_CPU_LIST <&CPU12>, <&CPU13>
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#elif (PLATFORM_CLUSTER_3_CORE_COUNT == 3)
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#define CLUSTER_3_CPU_LIST \
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CORE(0, 12) \
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CORE(1, 13) \
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CORE(2, 14)
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#define CLUSTER_3_CPUS \
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CPU(3, 0, 12, 30000) \
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CPU(3, 1, 13, 30100) \
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CPU(3, 2, 14, 30200)
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#define CLUSTER_3_DSU_PMU_CPU_LIST <&CPU12>, <&CPU13>, <&CPU14>
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#elif (PLATFORM_CLUSTER_3_CORE_COUNT == 4)
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#define CLUSTER_3_CPU_LIST \
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CORE(0, 12) \
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CORE(1, 13) \
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CORE(2, 14) \
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CORE(3, 15)
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#define CLUSTER_3_CPUS \
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CPU(3, 0, 12, 30000) \
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CPU(3, 1, 13, 30100) \
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CPU(3, 2, 14, 30200) \
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CPU(3, 3, 15, 30300)
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#define CLUSTER_3_DSU_PMU_CPU_LIST <&CPU12>, <&CPU13>, <&CPU14>, <&CPU15>
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#endif
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#define CLUSTER_0_CPU_MAP \
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cluster0 { \
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CLUSTER_0_CPU_LIST \
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};
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#define CLUSTER_0_DSU_PMU \
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CLUSTER_DSU_PMU(0, \
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CLUSTER_0_DSU_PMU_CPU_LIST, \
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CLUSTER_0_DSU_PMU_INTERRUPT_MAP)
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#if (PLATFORM_CLUSTER_1_CORE_COUNT >= 1)
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#define CLUSTER_1_CPU_MAP \
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cluster1 { \
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CLUSTER_1_CPU_LIST \
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};
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#define CLUSTER_1_DSU_PMU \
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CLUSTER_DSU_PMU(1, \
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CLUSTER_1_DSU_PMU_CPU_LIST, \
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CLUSTER_1_DSU_PMU_INTERRUPT_MAP)
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#endif
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#if (PLATFORM_CLUSTER_2_CORE_COUNT >= 1)
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#define CLUSTER_2_CPU_MAP \
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cluster2 { \
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CLUSTER_2_CPU_LIST \
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};
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#define CLUSTER_2_DSU_PMU \
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CLUSTER_DSU_PMU(2, \
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CLUSTER_2_DSU_PMU_CPU_LIST, \
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CLUSTER_2_DSU_PMU_INTERRUPT_MAP)
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#endif
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#if (PLATFORM_CLUSTER_3_CORE_COUNT >= 1)
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#define CLUSTER_3_CPU_MAP \
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cluster3 { \
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CLUSTER_3_CPU_LIST \
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};
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#define CLUSTER_3_DSU_PMU \
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CLUSTER_DSU_PMU(3, \
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CLUSTER_3_DSU_PMU_CPU_LIST, \
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CLUSTER_3_DSU_PMU_INTERRUPT_MAP)
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#endif
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/* Max 4 clusters */
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#if (PLAT_ARM_CLUSTER_COUNT == 1)
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#define CPU_MAP \
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cpu-map { \
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CLUSTER_0_CPU_MAP \
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};
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#define CPUS \
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CLUSTER_0_CPUS
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#define DSU_PMU \
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CLUSTER_0_DSU_PMU
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#define L3_CACHE \
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CLUSTER_L3_CACHE(0)
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#elif (PLAT_ARM_CLUSTER_COUNT == 2)
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#define CPU_MAP \
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cpu-map { \
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CLUSTER_0_CPU_MAP \
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CLUSTER_1_CPU_MAP \
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};
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#define CPUS \
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CLUSTER_0_CPUS \
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CLUSTER_1_CPUS
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#define DSU_PMU \
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CLUSTER_0_DSU_PMU \
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CLUSTER_1_DSU_PMU
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#define L3_CACHE \
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CLUSTER_L3_CACHE(0) \
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CLUSTER_L3_CACHE(1)
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#elif (PLAT_ARM_CLUSTER_COUNT == 3)
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#define CPU_MAP \
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cpu-map { \
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CLUSTER_0_CPU_MAP \
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CLUSTER_1_CPU_MAP \
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CLUSTER_2_CPU_MAP \
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};
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#define CPUS \
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CLUSTER_0_CPUS \
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CLUSTER_1_CPUS \
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CLUSTER_2_CPUS
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#define DSU_PMU \
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CLUSTER_0_DSU_PMU \
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CLUSTER_1_DSU_PMU \
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CLUSTER_2_DSU_PMU
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#define L3_CACHE \
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CLUSTER_L3_CACHE(0) \
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CLUSTER_L3_CACHE(1) \
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CLUSTER_L3_CACHE(2)
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#elif (PLAT_ARM_CLUSTER_COUNT == 4)
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#define CPU_MAP \
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cpu-map { \
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CLUSTER_0_CPU_MAP \
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CLUSTER_1_CPU_MAP \
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CLUSTER_2_CPU_MAP \
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CLUSTER_3_CPU_MAP \
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};
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#define CPUS \
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CLUSTER_0_CPUS \
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CLUSTER_1_CPUS \
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CLUSTER_2_CPUS \
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CLUSTER_3_CPUS
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#define DSU_PMU \
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CLUSTER_0_DSU_PMU \
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CLUSTER_1_DSU_PMU \
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CLUSTER_2_DSU_PMU \
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CLUSTER_3_DSU_PMU
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#define L3_CACHE \
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CLUSTER_L3_CACHE(0) \
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CLUSTER_L3_CACHE(1) \
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CLUSTER_L3_CACHE(2) \
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CLUSTER_L3_CACHE(3)
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#endif /* PLAT_ARM_CLUSTER_COUNT */
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#endif /* RDASPEN_DEFS_DTSI */
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