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Arvind Ram Prakash
f396aec85a
This patch adds support for FEAT_IDTE3, which introduces support
for handling the trapping of Group 3 and Group 5 (only GMID_EL1)
registers to EL3 (unless trapped to EL2). IDTE3 allows EL3 to
modify the view of ID registers for lower ELs, and this capability
is used to disable fields of ID registers tied to disabled features.
The ID registers are initially read as-is and stored in context.
Then, based on the feature enablement status for each world, if a
particular feature is disabled, its corresponding field in the
cached ID register is set to Res0. When lower ELs attempt to read
an ID register, the cached ID register value is returned. This
allows EL3 to prevent lower ELs from accessing feature-specific
system registers that are disabled in EL3, even though the hardware
implements them.
The emulated ID register values are stored primarily in per-world
context, except for certain debug-related ID registers such as
ID_AA64DFR0_EL1 and ID_AA64DFR1_EL1, which are stored in the
cpu_data and are unique to each PE. This is done to support feature
asymmetry that is commonly seen in debug features.
FEAT_IDTE3 traps all Group 3 ID registers in the range
op0 == 3, op1 == 0, CRn == 0, CRm == {2–7}, op2 == {0–7} and the
Group 5 GMID_EL1 register. However, only a handful of ID registers
contain fields used to detect features enabled in EL3. Hence, we
only cache those ID registers, while the rest are transparently
returned as is to the lower EL.
This patch updates the CREATE_FEATURE_FUNCS macro to generate
update_feat_xyz_idreg_field() functions that disable ID register
fields on a per-feature basis. The enabled_worlds scope is used to
disable ID register fields for security states where the feature is
not enabled.
This EXPERIMENTAL feature is controlled by the ENABLE_FEAT_IDTE3
build flag and is currently disabled by default.
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I5f998eeab81bb48c7595addc5595313a9ebb96d5
529 lines
18 KiB
C
529 lines
18 KiB
C
/*
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* Copyright (c) 2022-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_features.h>
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#include <common/debug.h>
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#include <common/feat_detect.h>
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#include <plat/common/platform.h>
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static bool detection_done[PLATFORM_CORE_COUNT] = { false };
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/*******************************************************************************
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* This section lists the wrapper modules for each feature to evaluate the
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* feature states (FEAT_STATE_ALWAYS and FEAT_STATE_CHECK) and perform
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* necessary action as below:
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*
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* It verifies whether the FEAT_XXX (eg: FEAT_SB) is supported by the PE or not.
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* Without this check an exception would occur during context save/restore
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* routines, if the feature is enabled but not supported by PE.
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******************************************************************************/
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#define feat_detect_panic(a, b) ((a) ? (void)0 : feature_panic(b))
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/*******************************************************************************
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* Function : feature_panic
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* Customised panic function with error logging mechanism to list the feature
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* not supported by the PE.
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******************************************************************************/
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static inline void feature_panic(char *feat_name)
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{
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ERROR("FEAT_%s not supported by the PE\n", feat_name);
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panic();
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}
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/*******************************************************************************
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* Function : check_feature
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* Check for a valid combination of build time flags (ENABLE_FEAT_xxx) and
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* feature availability on the hardware. <min> is the smallest feature
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* ID field value that is required for that feature.
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* Triggers a panic later if a feature is forcefully enabled, but not
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* available on the PE. Also will panic if the hardware feature ID field
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* is larger than the maximum known and supported number, specified by <max>.
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*
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* We force inlining here to let the compiler optimise away the whole check
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* if the feature is disabled at build time (FEAT_STATE_DISABLED).
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******************************************************************************/
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static inline bool __attribute((__always_inline__))
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check_feature(int state, unsigned long field, const char *feat_name,
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unsigned int min, unsigned int max)
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{
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if (state == FEAT_STATE_ALWAYS && field < min) {
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ERROR("FEAT_%s not supported by the PE\n", feat_name);
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return true;
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}
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if (state >= FEAT_STATE_ALWAYS && field > max) {
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ERROR("FEAT_%s is version %ld, but is only known up to version %d\n",
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feat_name, field, max);
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return true;
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}
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return false;
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}
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static unsigned int read_feat_rng_trap_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT,
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ID_AA64PFR1_EL1_RNDR_TRAP_MASK);
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}
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static unsigned int read_feat_bti_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_BT_SHIFT,
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ID_AA64PFR1_EL1_BT_MASK);
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}
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static unsigned int read_feat_sb_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT,
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ID_AA64ISAR1_SB_MASK);
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}
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static unsigned int read_feat_csv2_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2_SHIFT,
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ID_AA64PFR0_CSV2_MASK);
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}
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static unsigned int read_feat_debugv8p9_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_DEBUGVER_SHIFT,
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ID_AA64DFR0_DEBUGVER_MASK);
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}
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static unsigned int read_feat_pmuv3_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT,
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ID_AA64DFR0_PMUVER_MASK);
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}
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static unsigned int read_feat_vhe_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE_SHIFT,
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ID_AA64MMFR1_EL1_VHE_MASK);
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}
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static unsigned int read_feat_sve_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE_SHIFT,
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ID_AA64PFR0_SVE_MASK);
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}
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static unsigned int read_feat_ras_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS_SHIFT,
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ID_AA64PFR0_RAS_MASK);
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}
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static unsigned int read_feat_dit_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT_SHIFT,
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ID_AA64PFR0_DIT_MASK);
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}
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static unsigned int read_feat_amu_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU_SHIFT,
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ID_AA64PFR0_AMU_MASK);
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}
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static unsigned int read_feat_mpam_version(void)
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{
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return (unsigned int)((((read_id_aa64pfr0_el1() >>
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ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
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((read_id_aa64pfr1_el1() >>
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ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
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}
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static unsigned int read_feat_nv_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV_SHIFT,
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ID_AA64MMFR2_EL1_NV_MASK);
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}
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static unsigned int read_feat_sel2_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2_SHIFT,
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ID_AA64PFR0_SEL2_MASK);
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}
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static unsigned int read_feat_trf_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT_SHIFT,
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ID_AA64DFR0_TRACEFILT_MASK);
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}
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static unsigned int get_armv8_5_mte_support(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_MTE_SHIFT,
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ID_AA64PFR1_EL1_MTE_MASK);
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}
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static unsigned int read_feat_rng_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR_SHIFT,
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ID_AA64ISAR0_RNDR_MASK);
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}
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static unsigned int read_feat_fgt_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT_SHIFT,
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ID_AA64MMFR0_EL1_FGT_MASK);
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}
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static unsigned int read_feat_ecv_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV_SHIFT,
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ID_AA64MMFR0_EL1_ECV_MASK);
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}
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static unsigned int read_feat_twed_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED_SHIFT,
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ID_AA64MMFR1_EL1_TWED_MASK);
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}
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static unsigned int read_feat_hcx_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX_SHIFT,
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ID_AA64MMFR1_EL1_HCX_MASK);
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}
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static unsigned int read_feat_ls64_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_LS64_SHIFT,
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ID_AA64ISAR1_LS64_MASK);
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}
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static unsigned int read_feat_aie_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_AIE_SHIFT,
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ID_AA64MMFR3_EL1_AIE_MASK);
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}
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static unsigned int read_feat_pfar_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_PFAR_SHIFT,
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ID_AA64PFR1_EL1_PFAR_MASK);
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}
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static unsigned int read_feat_tcr2_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX_SHIFT,
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ID_AA64MMFR3_EL1_TCRX_MASK);
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}
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static unsigned int read_feat_s2pie_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE_SHIFT,
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ID_AA64MMFR3_EL1_S2PIE_MASK);
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}
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static unsigned int read_feat_s1pie_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE_SHIFT,
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ID_AA64MMFR3_EL1_S1PIE_MASK);
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}
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static unsigned int read_feat_s2poe_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE_SHIFT,
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ID_AA64MMFR3_EL1_S2POE_MASK);
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}
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static unsigned int read_feat_s1poe_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE_SHIFT,
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ID_AA64MMFR3_EL1_S1POE_MASK);
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}
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static unsigned int read_feat_brbe_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE_SHIFT,
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ID_AA64DFR0_BRBE_MASK);
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}
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static unsigned int read_feat_trbe_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER_SHIFT,
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ID_AA64DFR0_TRACEBUFFER_MASK);
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}
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static unsigned int read_feat_sme_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME_SHIFT,
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ID_AA64PFR1_EL1_SME_MASK);
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}
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static unsigned int read_feat_gcs_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS_SHIFT,
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ID_AA64PFR1_EL1_GCS_MASK);
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}
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static unsigned int read_feat_rme_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_FEAT_RME_SHIFT,
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ID_AA64PFR0_FEAT_RME_MASK);
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}
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static unsigned int read_feat_pan_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN_SHIFT,
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ID_AA64MMFR1_EL1_PAN_MASK);
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}
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static unsigned int read_feat_mtpmu_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT,
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ID_AA64DFR0_MTPMU_MASK);
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}
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static unsigned int read_feat_the_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_THE_SHIFT,
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ID_AA64PFR1_EL1_THE_MASK);
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}
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static unsigned int read_feat_sctlr2_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_SCTLR2_SHIFT,
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ID_AA64MMFR3_EL1_SCTLR2_MASK);
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}
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static unsigned int read_feat_d128_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_D128_SHIFT,
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ID_AA64MMFR3_EL1_D128_MASK);
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}
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static unsigned int read_feat_gcie_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_GCIE_SHIFT,
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ID_AA64PFR2_EL1_GCIE_MASK);
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}
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static unsigned int read_feat_ebep_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64dfr1_el1(), ID_AA64DFR1_EBEP_SHIFT,
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ID_AA64DFR1_EBEP_MASK);
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}
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static unsigned int read_feat_fpmr_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_FPMR_SHIFT,
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ID_AA64PFR2_EL1_FPMR_MASK);
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}
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static unsigned int read_feat_mops_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_EL1_MOPS_SHIFT,
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ID_AA64ISAR2_EL1_MOPS_MASK);
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}
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static unsigned int read_feat_fgwte3_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr4_el1(), ID_AA64MMFR4_EL1_FGWTE3_SHIFT,
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ID_AA64MMFR4_EL1_FGWTE3_MASK);
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}
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static unsigned int read_feat_cpa_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64isar3_el1(),
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ID_AA64ISAR3_EL1_CPA_SHIFT,
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ID_AA64ISAR3_EL1_CPA_MASK);
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}
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static unsigned int read_feat_clrbhb_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_CLRBHB_SHIFT,
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ID_AA64ISAR2_CLRBHB_MASK);
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}
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static unsigned int read_feat_rme_gdi_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr4_el1(),
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ID_AA64MMFR4_EL1_RME_GDI_SHIFT,
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ID_AA64MMFR4_EL1_RME_GDI_MASK);
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}
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static unsigned int read_feat_idte3_id_field(void)
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{
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return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_IDS_SHIFT,
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ID_AA64MMFR2_EL1_IDS_MASK);
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}
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/***********************************************************************************
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* TF-A supports many Arm architectural features starting from arch version
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* (8.0 till 8.7+). These features are mostly enabled through build flags. This
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* mechanism helps in validating these build flags in the early boot phase
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* either in BL1 or BL31 depending on the platform and assists in identifying
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* and notifying the features which are enabled but not supported by the PE.
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*
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* It reads all the enabled features ID-registers and ensures the features
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* are supported by the PE.
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* In case if they aren't it stops booting at an early phase and logs the error
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* messages, notifying the platforms about the features that are not supported.
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*
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* Further the procedure is implemented with a tri-state approach for each feature:
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* ENABLE_FEAT_xxx = 0 : The feature is disabled statically at compile time
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* ENABLE_FEAT_xxx = 1 : The feature is enabled and must be present in hardware.
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* There will be panic if feature is not present at cold boot.
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* ENABLE_FEAT_xxx = 2 : The feature is enabled but dynamically enabled at runtime
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* depending on hardware capability.
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*
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* For better readability, state values are defined with macros, namely:
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* { FEAT_STATE_DISABLED, FEAT_STATE_ALWAYS, FEAT_STATE_CHECK }, taking values
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* { 0, 1, 2 }, respectively, as their naming.
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**********************************************************************************/
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void detect_arch_features(unsigned int core_pos)
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{
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/* No need to keep checking after the first time for each core. */
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if (detection_done[core_pos]) {
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return;
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}
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bool tainted = false;
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/* v8.0 features */
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tainted |= check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(),
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"SB", 1, 1);
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tainted |= check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(),
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"CSV2_2", 2, 3);
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tainted |= check_feature(ENABLE_FEAT_CLRBHB, read_feat_clrbhb_id_field(),
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"CLRBHB", 1, 1);
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/*
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* Even though the PMUv3 is an OPTIONAL feature, it is always
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* implemented and Arm prescribes so. So assume it will be there and do
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* away with a flag for it. This is used to check minor PMUv3px
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* revisions so that we catch them as they come along
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*/
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tainted |= check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(),
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"PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P9);
|
|
|
|
/* v8.1 features */
|
|
tainted |= check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(),
|
|
"PAN", 1, 3);
|
|
tainted |= check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(),
|
|
"VHE", 1, 1);
|
|
|
|
/* v8.2 features */
|
|
tainted |= check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(),
|
|
"SVE", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(),
|
|
"RAS", 1, 2);
|
|
|
|
/* v8.3 features */
|
|
/* the PAuth fields are very complicated, no min/max is checked */
|
|
tainted |= check_feature(ENABLE_PAUTH, is_feat_pauth_present(),
|
|
"PAUTH", 1, 1);
|
|
|
|
/* v8.4 features */
|
|
tainted |= check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(),
|
|
"DIT", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(),
|
|
"AMUv1", 1, 2);
|
|
tainted |= check_feature(ENABLE_FEAT_MOPS, read_feat_mops_id_field(),
|
|
"MOPS", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(),
|
|
"MPAM", 1, 17);
|
|
tainted |= check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(),
|
|
"NV2", 2, 2);
|
|
tainted |= check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(),
|
|
"SEL2", 1, 1);
|
|
tainted |= check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(),
|
|
"TRF", 1, 1);
|
|
|
|
/* v8.5 features */
|
|
tainted |= check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(),
|
|
"MTE2", MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY);
|
|
tainted |= check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(),
|
|
"RNG", 1, 1);
|
|
tainted |= check_feature(ENABLE_BTI, read_feat_bti_id_field(),
|
|
"BTI", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(),
|
|
"RNG_TRAP", 1, 1);
|
|
|
|
/* v8.6 features */
|
|
tainted |= check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(),
|
|
"AMUv1p1", 2, 2);
|
|
tainted |= check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(),
|
|
"FGT", 1, 2);
|
|
tainted |= check_feature(ENABLE_FEAT_FGT2, read_feat_fgt_id_field(),
|
|
"FGT2", 2, 2);
|
|
tainted |= check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(),
|
|
"ECV", 1, 2);
|
|
tainted |= check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(),
|
|
"TWED", 1, 1);
|
|
|
|
/*
|
|
* even though this is a "DISABLE" it does confusingly perform feature
|
|
* enablement duties like all other flags here. Check it against the HW
|
|
* feature when we intend to diverge from the default behaviour
|
|
*/
|
|
tainted |= check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(),
|
|
"MTPMU", 1, 1);
|
|
|
|
/* v8.7 features */
|
|
tainted |= check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(),
|
|
"HCX", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_LS64_ACCDATA, read_feat_ls64_id_field(),
|
|
"LS64", 1, 3);
|
|
|
|
/* v8.9 features */
|
|
tainted |= check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(),
|
|
"TCR2", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(),
|
|
"S2PIE", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_S1PIE, read_feat_s1pie_id_field(),
|
|
"S1PIE", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_S2POE, read_feat_s2poe_id_field(),
|
|
"S2POE", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(),
|
|
"S1POE", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(),
|
|
"CSV2_3", 3, 3);
|
|
tainted |= check_feature(ENABLE_FEAT_DEBUGV8P9, read_feat_debugv8p9_id_field(),
|
|
"DEBUGV8P9", 11, 11);
|
|
tainted |= check_feature(ENABLE_FEAT_THE, read_feat_the_id_field(),
|
|
"THE", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_SCTLR2, read_feat_sctlr2_id_field(),
|
|
"SCTLR2", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_AIE, read_feat_aie_id_field(),
|
|
"AIE", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_PFAR, read_feat_pfar_id_field(),
|
|
"PFAR", 1, 1);
|
|
|
|
/* v9.0 features */
|
|
tainted |= check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(),
|
|
"BRBE", 1, 2);
|
|
tainted |= check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(),
|
|
"TRBE", 1, 1);
|
|
|
|
/* v9.2 features */
|
|
tainted |= check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(),
|
|
"SME", 1, 2);
|
|
tainted |= check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(),
|
|
"SME2", 2, 2);
|
|
tainted |= check_feature(ENABLE_FEAT_FPMR, read_feat_fpmr_id_field(),
|
|
"FPMR", 1, 1);
|
|
|
|
/* v9.3 features */
|
|
tainted |= check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(),
|
|
"D128", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_GCIE, read_feat_gcie_id_field(),
|
|
"GCIE", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_MPAM_PE_BW_CTRL,
|
|
is_feat_mpam_pe_bw_ctrl_present(),
|
|
"MPAM_PE_BW_CTRL", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_EBEP, read_feat_ebep_id_field(),
|
|
"EBEP", 1, 1);
|
|
|
|
/* v9.4 features */
|
|
tainted |= check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(),
|
|
"GCS", 1, 1);
|
|
tainted |= check_feature(ENABLE_RME, read_feat_rme_id_field(),
|
|
"RME", 1, 2);
|
|
tainted |= check_feature(ENABLE_FEAT_PAUTH_LR, is_feat_pauth_lr_present(),
|
|
"PAUTH_LR", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_FGWTE3, read_feat_fgwte3_id_field(),
|
|
"FGWTE3", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_CPA2, read_feat_cpa_id_field(),
|
|
"CPA2", 2, 2);
|
|
tainted |= check_feature(ENABLE_FEAT_RME_GDI, read_feat_rme_gdi_id_field(),
|
|
"RME_GDI", 1, 1);
|
|
tainted |= check_feature(ENABLE_FEAT_IDTE3, read_feat_idte3_id_field(),
|
|
"IDTE3", 2, 2);
|
|
|
|
if (tainted) {
|
|
panic();
|
|
}
|
|
|
|
detection_done[core_pos] = true;
|
|
}
|