mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2026-07-01 22:44:56 +00:00
Boyan Karatotev
04cf04c72d
BL2 has 3(!) entrypoints: 1) the regular EL1 entrypoint (once per AArch) 2) an EL3 entrypoint 3) an EL3 entrypoint with RME The EL1 and EL3 entrypoints are quite distinct so it's useful to keep them separate. But the EL3 and RME entrypoints are conceptually identical just configured differently and having slightly different assumptions (eg whether we can rely on BL1). So put them together with only the configuration as a difference. This has a few benefits: * makes the naming consistent - BL2 always runs at EL1, BL2_EL3 always runs at EL3. This is most important for the linker script. * paves the way for ENABLE_RME and RESET_TO_BL2 to coexist. * allows for more general refactors Currently, ENABLE_RME and RESET_TO_BL2 are mutually exclusive (from a makefile constraint) so the checks are simplified to one or the other as there is no danger of their simultaneous use. Change-Id: Iecffab2ff3a0bd7823f8277d9f66e22e4f42cc8c Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
136 lines
3.3 KiB
ArmAsm
136 lines
3.3 KiB
ArmAsm
/*
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* Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/bl_common.ld.h>
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#include <lib/xlat_tables/xlat_tables_defs.h>
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OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
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OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
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ENTRY(bl2_entrypoint)
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MEMORY {
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RAM (rwx): ORIGIN = BL2_BASE, LENGTH = BL2_LIMIT - BL2_BASE
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}
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SECTIONS {
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RAM_REGION_START = ORIGIN(RAM);
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RAM_REGION_LENGTH = LENGTH(RAM);
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. = BL2_BASE;
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ASSERT(. == ALIGN(PAGE_SIZE),
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"BL2_BASE address is not aligned on a page boundary.")
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#if SEPARATE_CODE_AND_RODATA
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.text . : {
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ASSERT(. == ALIGN(PAGE_SIZE),
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".text address is not aligned on a page boundary.");
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__TEXT_START__ = .;
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*bl2_entrypoint.o(.text*)
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*(SORT_BY_ALIGNMENT(.text*))
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*(.vectors)
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__TEXT_END_UNALIGNED__ = .;
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. = ALIGN(PAGE_SIZE);
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__TEXT_END__ = .;
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} >RAM
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/* .ARM.extab and .ARM.exidx are only added because Clang needs them */
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.ARM.extab . : {
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} >RAM
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.ARM.exidx . : {
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} >RAM
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.rodata . : {
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__RODATA_START__ = .;
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*(SORT_BY_ALIGNMENT(.rodata*))
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RODATA_COMMON
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__RODATA_END_UNALIGNED__ = .;
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. = ALIGN(PAGE_SIZE);
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__RODATA_END__ = .;
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} >RAM
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#else /* SEPARATE_CODE_AND_RODATA */
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.ro . : {
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ASSERT(. == ALIGN(PAGE_SIZE),
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".ro address is not aligned on a page boundary.");
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__RO_START__ = .;
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*bl2_entrypoint.o(.text*)
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*(SORT_BY_ALIGNMENT(.text*))
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*(SORT_BY_ALIGNMENT(.rodata*))
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RODATA_COMMON
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*(.vectors)
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__RO_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked as read-only,
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* executable. No RW data from the next section must creep in. Ensure
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* that the rest of the current memory page is unused.
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*/
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. = ALIGN(PAGE_SIZE);
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__RO_END__ = .;
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} >RAM
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#endif /* SEPARATE_CODE_AND_RODATA */
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__RW_START__ = .;
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DATA_SECTION >RAM
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STACK_SECTION >RAM
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BSS_SECTION >RAM
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XLAT_TABLE_SECTION >RAM
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#if USE_COHERENT_MEM
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/*
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* The base address of the coherent memory section must be page-aligned to
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* guarantee that the coherent data are stored on their own pages and are
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* not mixed with normal data. This is required to set up the correct
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* memory attributes for the coherent data page tables.
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*/
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.coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
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__COHERENT_RAM_START__ = .;
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*(.tzfw_coherent_mem)
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__COHERENT_RAM_END_UNALIGNED__ = .;
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/*
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* Memory page(s) mapped to this section will be marked as device
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* memory. No other unexpected data must creep in. Ensure the rest of
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* the current memory page is unused.
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*/
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. = ALIGN(PAGE_SIZE);
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__COHERENT_RAM_END__ = .;
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} >RAM
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#endif /* USE_COHERENT_MEM */
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__RW_END__ = .;
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__BL2_END__ = .;
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RAM_REGION_END = .;
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__BSS_SIZE__ = SIZEOF(.bss);
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#if USE_COHERENT_MEM
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__COHERENT_RAM_UNALIGNED_SIZE__ =
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__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
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#endif /* USE_COHERENT_MEM */
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ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
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}
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