Arvind Ram PrakashandGovindraj Raja c4c6eae4e0 feat(cm): add errata 2938996, 2726228 ...

This patch checks if the Errata 2938996(Cortex-A520) , 2726228(Cortex-X4)
applies to cores and if affected applies the errata workaround which
disables TRBE.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I53b037839820c8b3a869f393588302a365d5b97c
(cherry picked from commit 721249b0c0)
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

2024-10-23 16:44:37 -05:00

..

aarch64

fix(el3-runtime): restrict lower el EA handlers in FFH mode

2023-11-01 17:46:46 +00:00

bl31_context_mgmt.c

feat(rme): add context management changes for FEAT_RME

2021-10-05 18:41:35 +02:00

bl31_main.c

refactor(cm): move EL3 registers to global context

2023-10-31 11:18:42 +00:00

bl31_traps.c

feat(el3-runtime): handle traps for IMPDEF registers accesses

2023-04-30 11:04:59 +01:00

bl31.ld.S

feat(bl31): reuse SPM_MM specific defines for SPMC_AT_EL3

2023-10-12 10:44:34 +01:00

bl31.mk

feat(cm): add errata 2938996, 2726228

2024-10-23 16:44:37 -05:00

ehf.c

fix(gic600): workaround for Part 1 of GIC600 erratum 2384374

2024-03-08 19:04:52 +01:00

interrupt_mgmt.c

refactor(el3-runtime): plat_ic_has_interrupt_type returns bool

2023-09-25 17:09:15 -05:00