RNG #20
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#23 trng
airoha_en7523/kernel
Reference: airoha_en7523/kernel#20
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@merbanan if i use
devmem 0x1FAA182C, my system completely frozen, do you have the same problem?It is unclear if the EN7523 has the same rng. And if it has, the registers might be protected if the random number engine is started.
There are many unknowns and I think the correct solution is to just set the quality value to 900.
And to be clear I have not tested looking at the register myself. I am rebuilding my test setup so I can run more boards at the same time.
in dts have rng definitions
0e0066b175/target/linux/airoha/files/arch/arm/boot/dts/en7523_kernel_api.dtsi (L20-L24)0e0066b175/feeds/airoha/target/linux/airoha/files/arch/arm/boot/dts/en7523.dts (L37-L41)in xx520v v1 and xx230
4d76b59039/sdk/en7529/linux-4.4.115/arch/arm/boot/dts/en7523.dts (L287-L291)trng in en7523 needs enable with scu
74e58d4a82/econet_public/arch/arm/mach-econet/ecnt_scu.c (L792-L810)74e58d4a82/econet_public/arch/arm/mach-econet/ecnt_scu.c (L1319-L1321)Interesting, all this resolves to to the trng module. First the bus clock then the trng clock and then the trng_rc clock whatever that is.
Anyway all these should be enabled by default.
#define CR_CHIP_SCU_NP_BUS_DOM_CLK_GAT (CR_CHIP_SCU_BASE + 0x1E4)
#define CR_CHIP_SCU_NP_PER_DOM_CLK_GAT_1 (CR_CHIP_SCU_BASE + 0x1E8)
#define CR_CHIP_SCU_NP_PER_DOM_CLK_GAT_2 (CR_CHIP_SCU_BASE + 0x1EC)
You can check all these 3 with devmem.
1FA20000 is the Chip SCU base.
The clock driver should be completed with gating support. I doubt it will matter for power consumption though.
Ok, some clocks are gated. Long term these should be moved to the clock driver.
Sirherobrine23 referenced this issue2026-01-24 11:08:02 +00:00
I was able to read the rng data without the system crashing, but I had to separate the
scu, just like in the AN7581a7b3a01d79/target/linux/airoha/dts/en7523.dtsi (L263-L284)Bootlog