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bcm3390/dts/rg.cm1000-3390-base.dtsi
Joseph C. Lehner 9ddd6cf08f More stuff
2021-09-13 14:19:30 +02:00

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/ {
//Boot Assist
boot-assist {
compatible = "brcm,brcm-ba";
version = < 0x00020002 >;
interrupts = <0 23 0x4 0 24 0x4>;
reg = <0x0 0x04000000 0x0 0x05500000>, //Memory Region
<0x0 0xd3800000 0x0 0x80>, //CPU_COMM_REGS_CPUC
<0x0 0xd3881000 0x0 0x50>, //RG_TOP_CTRL
<0x0 0xd3880000 0x0 0x374>, //CM_TOP_CTRL
<0x0 0xf0410000 0x0 0x600>, //AON_CTRL
<0x0 0xf1500000 0x0 0x3fff>, //MEMC_0
<0x0 0xf1580000 0x0 0x3fff>, //MEMC_1
<0x0 0xd3890158 0x0 0x4>, //JTAG_OTP_UB:STATUS_16
<0x0 0xd2100000 0x0 0x300>; //LEAP_CTRL: Control registers
reg-names = "mem", "cpuc", "rgtop", "cmtop", "aon", "mc0", "mc1", "otp", "leap";
allow-user-map;
stb = < 0xFFFFFFFF 0 2 50 10 >; //start, size, # cpu, priority, latency
rg = < 0xFFFFFFFF 0 2 50 10 >; //start, size, # cpu, priority, latency
tp1 = < 0x08000000 0x01400000 >; //start, size
cm_xfer = < 0x09410000 0x20000 0x2 >; //start, size, count
leap = < 0x07F00000 0x100000>; //start, size
arm_boot_rom = <0x09430000 0x00010000>; //start, size
cm_atw = < 0x0 0x04000000 0x4000000 0x0 0x4807FFFC 0x0 0x0 0x0 >; //index, start, size, destination, client0-3
cm_dsp_atw = < 0x1 0x08000000 0x200000 0x7e00000 0x4804FFFC 0x0 0x0 0x0 >; //index, start, size, destination, client0-3
cm_boot_atw = < 0x2 0x09400000 0x10000 0x1fc00000 0x40000 0x0 0x0 0x0 >; //index, start, size, destination, client0-3
//arc=<memc, index, ubus, exclusive, start, end, r_clients[8], w_clients[8]>
};
brcm-mbox {
compatible = "brcm,brcm-mbox";
reg = <0x0 0xd3800080 0x0 0x80>, //MBOX_CPUC
<0x0 0xd3800000 0x0 0x80>; //CPU_COMM_REGS_CPUC
interrupts = <0 129 0x4>;
read = < 0x0000011F >; /* 0,1,2,3,4,8 */
write = < 0x000003E4 >; /* 2, 5, 6, 7, 8, 9 */
};
fpm@0xd3a00000 {
compatible = "brcm,fpm";
reg = <0x0 0x0BC00000 0x0 0x02000000>, /* Free Pool 0 */
<0x0 0xd3a00000 0x0 0x30133>; /* Registers */
// <0x0 0x86000000 0x0 0x02000000>; /* Free Pool 1 */
// <0x0 0x00000000 0x0 0x0>, /* Free Pool 1 */
// <0x0 0xd7e00000 0x0 0x1000>, /* UBUS capture engines 0 */
// <0x0 0xd3e00000 0x0 0x1000>; /* UBUS capture engines 1 */
interrupts = <0 127 0>;
init = <1>;
pool-alloc-weight = <1 1>;
pool-free-weight = <1 1>;
track-tokens = <1>;
track-on-err = <0>;
};
dqm: dqm@d3800000 {
compatible = "brcm,dqm";
reg = <0x0 0xd3800000 0x0 0xa580>;
interrupts = <0 129 0>;
dev-name = "cpucomm";
l1-irq-mask-offset = <0x0058>;
l1-irq-status-offset = <0x005c>;
l1-irq-dqm-mask = <0x00400000 0x00200000 0x00100000>;
token-offset = <0x1400>;
cfg-offset = <0x1c00 0x1c00 0x1c00>;
lwm-irq-mask-offset = <0x1cb4 0x1d44 0x1ddc>;
lwm-irq-status-offset = <0x1ca0 0x1d30 0x1dc8>;
ne-irq-mask-offset = <0x1c60 0x1cd8 0x1d6c>;
ne-irq-status-offset = <0x1c18 0x1cc4 0x1d58>;
ne-status-offset = <0x1c20 0x1cc8 0x1d5c>;
fpm-alloc-offset = <0x1df4 0x1df4 0x1df4>;
q-ctl-base-offset = <0x8000 0x8400 0x8800>;
q-data-base-offset = <0x9000 0x9400 0x9800>;
q-status-base-offset = <0x7400 0x7480 0x7500>;
q-mib-base-offset = <0xa000 0xa200 0xa400>;
q-count = <96>;
cfg-qsm = <1>;
qsm-size = <0x2fc0>; /* Bx and beyond top 256 bytes reserved for random seed created by bootrom */
#qsm-alloc-cells = <4>;
/* set all Q's to offload due to chip bug in Ax where non-offload doesn't work */
/* do not use 3rd bank (Q #'s 64-95) due to chip bug in some Ax mask and other register reads & writes */
/* Q #, # words/element, # elements (depth), offload(1)/non-offload(0) */
qsm-allocation = < 2 4 8 1 /* RPC RG-->CM */
3 4 8 1 /* RPC RG<--CM */
8 4 8 1 /* RPC DECT-->CM */
9 4 8 1 /* RPC DECT<--CM */
10 2 16 1 /* Private Network DECT-->CM */
11 2 16 1 /* Private Network DECT<--CM */
14 2 16 1 /* Private Network RG (bridge)-->CM */
15 2 16 1 /* Private Network RG (bridge)<--CM */
20 4 8 1 /* RPC SVM-->CM */
21 4 8 1 /* RPC SVM<--CM */
32 2 64 1 /* RG DS Forward (RG-->Runner) */
33 2 2048 1 /* WiFi US Forward (WiFi-->Runner) */
34 2 64 1 /* RG DS Egress (RG-->Runner) */
35 2 64 1 /* RG US Egress (RG-->Runner) */
36 2 64 1 /* STB DS Forward (STB-->Runner) */
37 2 64 1 /* STB US Forward (STB-->Runner) */
38 2 64 1 /* STB DS Egress (STB-->Runner) */
39 2 64 1 /* STB US Egress (STB-->Runner) */
40 2 64 1 /* DFAP DS Forward (DFAP-->Runner) */
41 2 64 1 /* DFAP US Forward (DFAP-->Runner) */
42 2 64 1 /* DFAP DS Egress (DFAP-->Runner) */
43 2 64 1 /* DFAP US Egress (DFAP-->Runner) */
44 2 64 1 /* Viper DS Forward (DFAP-->Runner) */
45 2 64 1 /* Viper US Forward (DFAP-->Runner) */
46 2 64 1 /* Viper DS Egress (DFAP-->Runner) */
47 2 64 1 /* Viper US Egress (DFAP-->Runner) */
48 4 256 1 /* RG Exception 0 (Runner-->RG) */
49 4 256 1 /* RG Exception 1 (Runner-->RG) */
50 4 256 1 /* RG Exception 2 (Runner-->RG) */
51 4 256 1 /* RG Exception 3 (Runner-->RG) */
52 4 256 1 /* RG Exception 4 (Runner-->RG) */
53 4 256 1 /* RG Exception 5 (Runner-->RG) */
54 4 256 1 /* RG Exception 6 (Runner-->RG) */
55 4 256 1 /* RG Exception 7 (Runner-->RG) */
56 4 4000 1 /* WiFi 0 Rx (Runner-->WiFi) */
57 4 4000 1 /* WiFi 0 Rx (Runner-->WiFi) */
58 4 4000 1 /* WiFi 1 Rx (Runner-->WiFi) */
59 4 4000 1 >; /* WiFi 1 Rx (Runner-->WiFi) */
};
rpcrgcm: rpcrgcm {
compatible = "brcm,itc-rpc";
dev-name = "rg-cm";
dqm = "cpucomm";
tx-q = <2>;
rx-q = <3>;
};
rpcsvmcm: rpcsvmcm {
compatible = "brcm,itc-rpc";
dev-name = "svm-cm";
dqm = "cpucomm";
tx-q = <20>;
rx-q = <21>;
};
qchan0: q-channel0 {
dev-name = "fap-exception";
#tx-q-cells = <4>;
/* DQM device, Q#, Priority US/DS */
tx-q = "cpucomm", "35", "0", "upstream", /* RG upstream egress */
"cpucomm", "34", "0", "downstream"; /* RG downstream egress */
#rx-q-cells = <3>;
/* DQM device, Q#, Priority */
rx-q = "cpucomm", "48", "0"; /* Runner-->RG 0 */
type = "fap-exception";
q-msg-fmt = "runner";
};
qchan1: q-channel1 {
dev-name = "cm-private";
#tx-q-cells = <3>;
/* DQM device, Q#, Priority US/DS */
tx-q = "cpucomm", "14", "0"; /* RG-->CM */
#rx-q-cells = <3>;
/* DQM device, Q#, Priority */
rx-q = "cpucomm", "15", "0"; /* CM-->RG */
type = "point-to-point";
q-msg-fmt = "gfap";
};
priv0 { /* RG <--> CM private */
compatible = "brcm,dqnet";
channel = <&qchan1>;
dev-name = "priv0";
demux = "none";
link-type = "rpc";
rpc-channel = <&rpcrgcm>;
};
eth0: ethernet0 {
compatible = "brcm,dqnet";
channel = <&qchan0>;
dev-name = "eth0";
if-id = <2>; /* rdpa_if_lan0 */
if-sub-id = <0>; /* if-sub-id must match the first column in phy-port node */
demux = "subid";
link-type = "switch";
brcm-tag = <1>;
};
eth1: ethernet1 {
compatible = "brcm,dqnet";
channel = <&qchan0>;
dev-name = "eth1";
if-id = <3>; /* rdpa_if_lan1 */
if-sub-id = <1>; /* if-sub-id must match the first column in phy-port node */
demux = "subid";
link-type = "switch";
brcm-tag = <1>;
};
/* Mel, 20151209, Disable eth2~eth3 */
// eth2: ethernet2 {
// compatible = "brcm,dqnet";
// channel = <&qchan0>;
// dev-name = "eth2";
// if-id = <4>; /* rdpa_if_lan2 */
// if-sub-id = <2>; /* if-sub-id must match the first column in phy-port node */
// demux = "subid";
// link-type = "switch";
// brcm-tag = <1>;
// };
//
// eth3: ethernet3 {
// compatible = "brcm,dqnet";
// channel = <&qchan0>;
// dev-name = "eth3";
// if-id = <5>; /* rdpa_if_lan3 */
// if-sub-id = <3>; /* if-sub-id must match the first column in phy-port node */
// demux = "subid";
// link-type = "switch";
// brcm-tag = <1>;
// };
/* Mel, 20151209, End */
cm0 {
compatible = "brcm,dqnet";
channel = <&qchan0>;
dev-name = "cm0";
if-id = <0>; /* rdpa_if_wan0 */
demux = "subid";
link-type = "rpc";
rpc-channel = <&rpcrgcm>;
};
miimdiomux: miimdiomux@d3c026a0 {
compatible = "brcm,miimdiomux3390";
reg = <0 0xd3c026a0 0 0x4>;
rgmii0-tx-select = "unimac";
rgmii1-tx-select = "unimac";
p7-rx-select = "runner";
p4-rx-select = "moca";
unimac-rx-select = "rgmii1";
unimac-mdio-select = "mdio0";
switch-mdio-select = "mdio1";
};
unimac_mdio: mdio@d040062c {
compatible = "brcm,unimac-mdio";
reg = <0 0xd040062c 0 0x8>;
reg-names = "mdio";
#size-cells = <1>;
#address-cells = <0>;
};
switch_mdio: mdio@d4e403c0 {
compatible = "brcm,unimac-mdio";
reg = <0 0xd4e403c0 0 0x8>;
reg-names = "mdio";
#size-cells = <1>;
#address-cells = <0>;
};
ethsw: ethsw@d4e00000 {
compatible = "brcm,ethsw";
reg = <0x0 0xd4e00000 0x0 0x42000>,
<0x0 0xd3c00000 0x0 0x2800>;
interrupts = <0 113 0>,
<0 114 0>;
dev-name = "ethsw";
phy-port = <0 2>,
<1 3>,
<2 4>,
<3 5>;
mii-port = <4 0 1000>;
imp-port = <5 2000>,
<7 2000>,
<8 2000>;
eee-support = <1>;
high-speed-imp = <1>;
};
runner: runner@0xd5000000 {
compatible = "brcm,rdpa_cm";
reg = <0x0 0xd5000000 0x0 0x000fc460>, /* Registers */
<0x0 0x09c00000 0x0 0x02000000>, /* Runner Extra Memory 0 */
<0x0 0x00000000 0x0 0x00000000>, /* Runner Extra Memory 1 */
<0x0 0x09500000 0x0 0x00700000>; /* Runner NAT Cache */
freq = <800>; /* MHz */
lag-ports = < 0 1 2 >;
};
upg_fixed: upg_fixed {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <27000000>;
};
suntop_pmx: pinmux@f0404100 {
compatible = "pinctrl-single";
reg = <0 0xf04040a4 0 0xc4>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x1>;
pinctrl-names = "default";
};
pmb@0xd3c03100 {
compatible = "brcm,pmb";
reg = <0 0xd3c03100 0 0x50000>;
#address-cells = <0>;
#size-cells = <1>;
direct-access;
pbcm@0x7 {
compatible = "brcm,bpcm";
reg = <0x7>;
dev-name = "bpcm-fpm";
zones = <1>;
boot-on;
};
pbcm@0x8 {
compatible = "brcm,bpcm";
reg = <0x8>;
dev-name = "bpcm-cpuc";
zones = <1>;
boot-on;
};
pbcm@0xb {
compatible = "brcm,bpcm";
reg = <0xb>;
dev-name = "bpcm-unimac";
zones = <1>;
boot-on;
};
};
pmb@0xf10b0f00 {
compatible = "brcm,pmb";
reg = <0 0xf10b0f00 0 0x10>;
#address-cells = <0>;
#size-cells = <1>;
version=<2>;
pbcm@0x0 {
compatible = "brcm,bpcm";
reg = <0x0>;
dev-name = "bpcm-rdp";
zones = <2>;
boot-on;
};
};
};
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