mirror of
https://github.com/jclehner/bcm3390.git
synced 2025-01-31 00:31:35 +00:00
77 lines
1.9 KiB
Plaintext
77 lines
1.9 KiB
Plaintext
/dts-v1/;
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/ {
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model = "Broadcom CM (bcm93390z0wvgs)";
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compatible = "brcm,bcm93390z0wvgs",
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"brcm,bcm3390z0",
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"brcm,bcm3390",
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"brcm,brcmcm", "brcm,brcmstb";
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subsystem = "rg";
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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interrupt-parent = <&gic>;
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};
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/include/ "rg.3390b0-bolt.dtsi"
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/include/ "rg.3390-base.dtsi"
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/include/ "rg.3390-wifi.dtsi"
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/include/ "rg.3390z0-bolt.dtsi"
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/********************************************************************
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* any nodes that appear below are platform specific additions and
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* replacements.
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* The dtc will add or replace any properties in the nodes
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* below to the same nodes that appear in include files above.
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* If the property does not exist in the node above it will be added.
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* If the property does exist it will replace it.
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********************************************************************/
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&wler_rfap {
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dev-names = "wl0 wl1";
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};
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&wifi_rfpwr {
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supply-names = "vreg-wl0-rf", "vreg-wl1-rf";
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/delete-property/vreg-wl2-rf-supply;
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};
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/ {
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/delete-node/vreg-wl2;
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/delete-node/vreg-wl2-rf;
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rdb {
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/delete-node/sdhci@f04a0100;
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/delete-node/sdhci@f04a0300;
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};
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aliases {
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/delete-property/sdhci0;
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/delete-property/sdhci1;
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};
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chosen {
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filename = "rg.3390z0-wvgs.dtb";
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};
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};
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&rsvd_rg_memc0 {
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reg = <0x0 0x4000000 0x0 0x09c00000>;
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};
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&fpm {
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reg = <0x0 0x0bc00000 0x0 0x02000000>, /* Free Pool 0 */
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<0x0 0xd3a00000 0x0 0x30133>, /* Registers */
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<0x0 0x00000000 0x0 0x00000000>; /* Free Pool 1 */
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chunk-size = <512>;
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net-buf-head-pad = <240>;
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net-buf-tail-pad = <256>;
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};
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&runner {
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reg = <0x0 0xd5000000 0x0 0x000fc460>, /* Registers */
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<0x0 0x09c00000 0x0 0x02000000>, /* Runner Extra Memory 0 */
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<0x0 0x00000000 0x0 0x00000000>, /* Runner Extra Memory 1 */
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<0x0 0x09500000 0x0 0x00700000>; /* Runner NAT Cache */
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freq = <800>; /* MHz */
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lag-ports = < 0 1 2 >;
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};
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