mirror of
https://github.com/jclehner/bcm3390.git
synced 2025-01-31 00:31:35 +00:00
520 lines
16 KiB
Plaintext
520 lines
16 KiB
Plaintext
/ {
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//Boot Assist
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bassist: ba {
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compatible = "brcm,brcm-ba";
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version = < 0x00020002 >;
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interrupts = <0 23 0x4 0 24 0x4>;
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reg = <0x0 0x04000000 0x0 0x05500000>, //Memory Region
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<0x0 0xd3800000 0x0 0x80>, //CPU_COMM_REGS_CPUC
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<0x0 0xd3881000 0x0 0x50>, //RG_TOP_CTRL
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<0x0 0xd3880000 0x0 0x374>, //CM_TOP_CTRL
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<0x0 0xf0410000 0x0 0x600>, //AON_CTRL
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<0x0 0xf1500000 0x0 0x3fff>, //MEMC_0
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<0x0 0xf1580000 0x0 0x3fff>, //MEMC_1
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<0x0 0xd3890158 0x0 0x8>, //JTAG_OTP_UB
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<0x0 0xd2100000 0x0 0x300>, //LEAP_CTRL: Control registers
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<0x0 0xd3c009c0 0x0 0x8>; //LED: Control registers
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reg-names = "mem", "cpuc", "rgtop", "cmtop", "aon", "mc0", "mc1", "otp", "leap", "leds";
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allow-user-map;
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stb = < 0xFFFFFFFF 0 2 50 10 >; //start, size, # cpu, priority, latency
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rg = < 0xFFFFFFFF 0 2 50 10 >; //start, size, # cpu, priority, latency
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tp1 = < 0x08000000 0x01400000 >; //start, size
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cm_xfer = < 0x09410000 0x20000 0x2 >; //start, size, count
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leap = < 0x07F00000 0x100000>; //start, size
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arm_boot_rom = <0x09430000 0x00010000>; //start, size
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cm_atw = < 0x0 0x04000000 0x4000000 0x0 0x4807FFFC 0x0 0x0 0x0 >; //index, start, size, destination, client0-3
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cm_dsp_atw = < 0x1 0x08000000 0x00400000 0x07c00000 0x4804FFFC 0x0 0x0 0x0 >; //index, start, size, destination, client0-3
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cm_boot_atw = < 0x2 0x09400000 0x10000 0x1fc00000 0x40000 0x0 0x0 0x0 >; //index, start, size, destination, client0-3
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leds = < 0xd3c009c0 0x8>; //start, size
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//arc=<memc, index, ubus, exclusive, start, end, r_clients[8], w_clients[8]>
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rg-batt-mode = "off";
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};
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mbox: mbox {
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compatible = "brcm,brcm-mbox";
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reg = <0x0 0xd3800080 0x0 0x80>, //MBOX_CPUC
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<0x0 0xd3800000 0x0 0x80>; //CPU_COMM_REGS_CPUC
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interrupts = <0 129 0x4>;
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read = < 0x0000011F >; /* 0,1,2,3,4,8 */
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write = < 0x000003E4 >; /* 2, 5, 6, 7, 8, 9 */
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};
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fpm: fpm@0xd3a00000 {
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compatible = "brcm,fpm";
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reg = <0x0 0x0ac00000 0x0 0x01000000>, /* Free Pool 0 */
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<0x0 0xd3a00000 0x0 0x30133>, /* Registers */
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<0x0 0x0cc00000 0x0 0x01000000>; /* Free Pool 1 */
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interrupts = <0 127 0>;
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init;
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pool-alloc-weight = <1 1>;
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pool-free-weight = <1 1>;
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track-tokens = <1>;
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track-on-err = <0>;
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/*
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* System-wide all FPM's used for network packets need to have space reserved
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* at the head and possibly tail of the buffer. The head and tail padding is only
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* required for network buffers. FPM buffers used for other purposes do not
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* require any padding. DOCSIS necessitates a small head padding while systems
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* with WiFi not only require a large head padding but also need tail padding.
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* The values specified in the "head-pad" and "tail-pad" parameters below are
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* available to other Linux drivers via an FPM driver API and to the rest of the
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* system (i.e. DOCSIS HW, network accelerators, etc) via an FPM scratch register.
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*
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* DOCSIS-only Head Padding = Reason
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* 32 Runner <--> DFAP header
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*
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* DOCSIS + WiFi Head Padding = Reason
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* 240 BRCM WiFi driver's head padding requirement
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*
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* DOCSIS + WiFi Tail Padding = Reason
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* 4 struct skb_shared_info alignment
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* + 40 sizeof(struct skb_shared_info) - sizeof(skb_frag_t array)
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* + 4 struct sk_buff alignment
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* + 200 sizeof(struct sk_buff)
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* + 8 sizeof(WLER_CNTXT) "wl_erouter context"
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*
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* Below we default to a DOCSIS-only head and tail pad and we let the WiFI include
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* file override these to larger values for the DOCSIS + WiFi platforms.
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*
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* The head and tail padding is also closely coupled with the FPM buffer chunk size
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* (256 or 512 bytes). 256 byte chunks can be used on DOCSIS-only systems because they
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* only require a small head padding which can be accomodated with a minimum-size 256 byte
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* buffer. This allows the FPM and Runner pools to be minimized (32MB per pool).
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* WiFi systems, however, require head and tail padding large enough that a 256 byte
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* buffer is insufficient for even the smallest packet so a 512 byte chunk size is used
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* which also ensures that FPM buffers of sufficient size to hold the largest possible
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* packets can be allocated. This larger chunk size also uses twice as much memory for
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* the FPM and Runner pools (64MB per pool).
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*
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* Because the memory required for the FPM and Runner pools varies with the chunk size
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* any changes to the chunk size necessitates changes to the pool addresses and sizes
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* specified in the FPM and Runner "reg" properties as well as the "reserved-memory" node.
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*/
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chunk-size = <256>;
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net-buf-head-pad = <16>;
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net-buf-tail-pad = <0>;
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lwm-watchdog-timeout = <300000>; /* 5 minutes */
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};
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dqm: dqm@d3800000 {
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compatible = "brcm,dqm";
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reg = <0x0 0xd3800000 0x0 0xa580>;
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interrupts = <0 129 0>;
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dev-name = "cpucomm";
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l1-irq-mask-offset = <0x0058>;
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l1-irq-status-offset = <0x005c>;
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l1-irq-dqm-mask = <0x00400000 0x00200000 0x00100000>;
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token-offset = <0x1400>;
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cfg-offset = <0x1c00 0x1c00 0x1c00>;
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lwm-irq-mask-offset = <0x1cb4 0x1d44 0x1ddc>;
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lwm-irq-status-offset = <0x1ca0 0x1d30 0x1dc8>;
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ne-irq-mask-offset = <0x1c60 0x1cd8 0x1d6c>;
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ne-irq-status-offset = <0x1c18 0x1cc4 0x1d58>;
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ne-status-offset = <0x1c20 0x1cc8 0x1d5c>;
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hwm-irq-mask-offset = <0x1c8c 0x1d20 0x1db4>;
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hwm-irq-status-offset = <0x1c78 0x1d0c 0x1da0>;
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tmr-irq-mask-offset = <0x1c4c 0x1cfc 0x1d90>;
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tmr-irq-status-offset = <0x1c38 0x1ce8 0x1d7c>;
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fpm-alloc-offset = <0x1df4 0x1df4 0x1df4>;
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q-ctl-base-offset = <0x8000 0x8400 0x8800>;
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q-tmr-base-offset = <0x2000 0x2100 0x2200>;
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q-data-base-offset = <0x9000 0x9400 0x9800>;
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q-status-base-offset = <0x7400 0x7480 0x7500>;
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q-mib-base-offset = <0xa000 0xa200 0xa400>;
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q-count = <96>;
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cfg-qsm = <1>;
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qsm-size = <0x2fc0>; /* Bx and beyond top 256 bytes reserved for random seed created by bootrom */
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#qsm-alloc-str-cells = <8>;
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/* Following Queues are reserved but not used */
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/* 36 : STB DS Forward (STB-->Runner) */
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/* 37 : STB US Forward (STB-->Runner) */
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/* 38 : STB DS Egress (STB-->Runner) */
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/* 39 : STB US Egress (STB-->Runner) */
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/* 44 : Viper DS Forward (DFAP-->Runner) */
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/* 45 : Viper US Forward (DFAP-->Runner) */
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/* 46 : Viper DS Egress (DFAP-->Runner) */
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/* Q #, # words/element, # elements (depth), offload(1)/non-offload(0), LWM, HWM, timeout(ns), Name */
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qsm-allocation-str = "2", "4", "8", "1", "2", "1", "0", "RPC RG-->CM",
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"3", "4", "8", "1", "2", "1", "0", "RPC RG<--CM",
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"6", "4", "8", "1", "2", "1", "0", "RPC STB-->CM",
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"7", "4", "8", "1", "2", "1", "0", "RPC STB<--CM",
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"8", "4", "8", "1", "2", "1", "0", "RPC DECT-->CM",
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"9", "4", "8", "1", "2", "1", "0", "RPC DECT<--CM",
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"14", "2", "16", "1", "4", "1", "0", "Private Network RG-->CM",
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"15", "2", "64", "1", "4", "1", "0", "Private Network RG<--CM",
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"20", "4", "8", "1", "2", "1", "0", "RPC SVM-->CM",
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"21", "4", "8", "1", "2", "1", "0", "RPC SVM<--CM",
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"32", "4", "64", "1", "16", "1", "0", "RG DS Forward (RG-->Runner)",
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"34", "4", "64", "1", "16", "1", "0", "RG DS Egress (RG-->Runner)",
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"35", "4", "64", "1", "16", "1", "0", "RG US Egress (RG-->Runner)",
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"47", "2", "4000", "1", "512", "1", "0", "SKB Prealloc (RG-->Runner)",
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"48", "4", "4000", "1", "64", "64", "1000", "RG Exception LAN (Runner-->RG)",
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"49", "4", "256", "1", "64", "1", "0", "RG Exception Ctl (Runner-->RG)",
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"50", "4", "4000", "1", "64", "64", "1000", "RG Exception WAN (Runner-->RG)",
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"51", "4", "4000", "1", "64", "64", "1000", "RG Expected 0 (Runner-->RG)",
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"52", "4", "4000", "1", "64", "64", "1000", "RG Expected 1 (Runner-->RG)",
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"53", "4", "4000", "1", "64", "64", "1000", "RG Expected 2 (Runner-->RG)",
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"54", "4", "4000", "1", "64", "64", "1000", "RG Expected 3 (Runner-->RG)",
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"55", "1", "4000", "1", "16", "1000", "0", "SKB Recycle (Runner-->RG)";
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};
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pwr: power {
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boot-state = "ac";
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};
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rpcrgcm: rpcrgcm {
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compatible = "brcm,itc-rpc";
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dev-name = "rg-cm";
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dqm = "cpucomm";
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tx-q = <2>;
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rx-q = <3>;
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};
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rpcsvmcm: rpcsvmcm {
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compatible = "brcm,itc-rpc";
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dev-name = "svm-cm";
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dqm = "cpucomm";
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tx-q = <20>;
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rx-q = <21>;
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};
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qchan0: q-channel0 {
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dev-name = "fap-exception";
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#tx-q-cells = <4>;
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/* DQM device, Q#, Priority US/DS */
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tx-q = "cpucomm", "35", "0", "upstream", /* RG upstream egress */
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"cpucomm", "34", "0", "downstream"; /* RG downstream egress */
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#rx-q-cells = <4>;
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/* DQM device, Q#, Priority */
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rx-q = "cpucomm", "49", "0", "control", /* Runner-->RG 0 */
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"cpucomm", "51", "1", "expected", /* Runner-->RG 1 */
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"cpucomm", "48", "2", "upstream", /* Runner-->RG 2 */
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"cpucomm", "50", "3", "downstream"; /* Runner-->RG 3 */
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type = "fap-exception";
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q-msg-fmt = "runner-fpm";
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};
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qchan1: q-channel1 {
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dev-name = "cm-private";
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#tx-q-cells = <3>;
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/* DQM device, Q#, Priority US/DS */
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tx-q = "cpucomm", "14", "0"; /* RG-->CM */
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#rx-q-cells = <3>;
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/* DQM device, Q#, Priority */
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rx-q = "cpucomm", "15", "0"; /* CM-->RG */
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type = "point-to-point";
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q-msg-fmt = "gfap-fpm";
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};
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rfapskb: rfapskb {
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compatible = "brcm,dqskb";
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dev-name = "dqskb-rfap";
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dqm = "cpucomm";
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tx-q = <47>;
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rx-q = <55>;
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};
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mdqmrx0: mdqmrx0 {
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compatible = "brcm,mdqm";
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dev-name = "mdqmrx0";
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dqm = "cpucomm";
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q-type = "rx";
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q-num = <56 57>;
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};
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mdqmrx1: mdqmrx1 {
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compatible = "brcm,mdqm";
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dev-name = "mdqmrx1";
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dqm = "cpucomm";
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q-type = "rx";
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q-num = <58 59>;
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};
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mdqmrx2: mdqmrx2 {
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compatible = "brcm,mdqm";
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dev-name = "mdqmrx2";
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dqm = "cpucomm";
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q-type = "rx";
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q-num = <60 61>;
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};
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mdqmtx: mdqmtx {
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compatible = "brcm,mdqm";
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dev-name = "mdqmtx";
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dqm = "cpucomm";
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q-type = "tx";
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q-num = <33>;
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};
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priv0: priv0 { /* RG <--> CM private */
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compatible = "brcm,dqnet";
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channel = <&qchan1>;
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dev-name = "priv0";
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demux = "none";
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link-type = "rpc";
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rpc-channel = <&rpcrgcm>;
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};
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eth0: ethernet0 {
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compatible = "brcm,dqnet";
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channel = <&qchan0>;
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dev-name = "eth0";
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if-id = <2>; /* rdpa_if_lan0 */
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if-sub-id = <0>; /* if-sub-id must match the first column in phy-port node */
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demux = "subid";
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link-type = "switch";
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connection-type = "internal";
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brcm-tag;
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};
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eth1: ethernet1 {
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compatible = "brcm,dqnet";
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channel = <&qchan0>;
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dev-name = "eth1";
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if-id = <3>; /* rdpa_if_lan1 */
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if-sub-id = <1>; /* if-sub-id must match the first column in phy-port node */
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demux = "subid";
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link-type = "switch";
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connection-type = "internal";
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brcm-tag;
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};
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eth2: ethernet2 {
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compatible = "brcm,dqnet";
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channel = <&qchan0>;
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dev-name = "eth2";
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if-id = <4>; /* rdpa_if_lan2 */
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if-sub-id = <2>; /* if-sub-id must match the first column in phy-port node */
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demux = "subid";
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link-type = "switch";
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connection-type = "internal";
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brcm-tag;
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};
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eth3: ethernet3 {
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compatible = "brcm,dqnet";
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channel = <&qchan0>;
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dev-name = "eth3";
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if-id = <5>; /* rdpa_if_lan3 */
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if-sub-id = <3>; /* if-sub-id must match the first column in phy-port node */
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demux = "subid";
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link-type = "switch";
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connection-type = "internal";
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brcm-tag;
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};
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cm0: cm0 {
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compatible = "brcm,dqnet";
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channel = <&qchan0>;
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dev-name = "cm0";
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if-id = <0>; /* rdpa_if_wan0 */
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demux = "subid";
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link-type = "rpc";
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rpc-channel = <&rpcrgcm>;
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};
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miimdiomux: miimdiomux@d3c026a0 {
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compatible = "brcm,miimdiomux3390";
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reg = <0 0xd3c026a0 0 0x4>;
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rgmii0-tx-select = "unimac";
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rgmii1-tx-select = "zero";
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p7-rx-select = "runner";
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p4-rx-select = "moca";
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unimac-rx-select = "rgmii0";
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unimac-mdio-select = "mdio0";
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switch-mdio-select = "mdio1";
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};
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unimac_mdio: mdio@d040062c {
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compatible = "brcm,unimac-mdio";
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dev-name = "UniMAC MII bus";
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reg = <0 0xd040062c 0 0x8>;
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reg-names = "unimac_mdio";
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#size-cells = <1>;
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#address-cells = <0>;
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};
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switch_mdio: mdio@d4e403c0 {
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compatible = "brcm,unimac-mdio";
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dev-name = "Switch MDIO bus";
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reg = <0 0xd4e403c0 0 0x8>;
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reg-names = "switch_mdio";
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#size-cells = <1>;
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#address-cells = <0>;
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sw_p0_phy: phy@8 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <8>;
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phy-mode = "rgmii";
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};
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sw_p1_phy: phy@9 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <9>;
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phy-mode = "rgmii";
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};
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sw_p2_phy: phy@10 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <10>;
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phy-mode = "rgmii";
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};
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sw_p3_phy: phy@11 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <11>;
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phy-mode = "rgmii";
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};
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};
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ethsw: ethsw@d4e00000 {
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compatible = "brcm,ethsw";
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reg = <0x0 0xd4e00000 0x0 0x42000>,
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<0x0 0xd3c009c0 0x0 0x2c>;
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interrupts = <0 113 0>,
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<0 114 0>;
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dev-name = "ethsw";
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imp-port = <5 2000>,
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<7 2000>,
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<8 2000>;
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eee-support = <1>;
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high-speed-imp = <1>;
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phy-handles = <&sw_p0_phy>,
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<&sw_p1_phy>,
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<&sw_p2_phy>,
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<&sw_p3_phy>;
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subid-port-offset = <0>;
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#size-cells = <1>;
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#address-cells = <0>;
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};
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runner: runner@0xd5000000 {
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compatible = "brcm,rdpa_cm";
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reg = <0x0 0xd5000000 0x0 0x000fc460>, /* Registers */
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<0x0 0x09c00000 0x0 0x01000000>, /* Runner Extra Memory 0 */
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<0x0 0x0bc00000 0x0 0x01000000>, /* Runner Extra Memory 1 */
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<0x0 0x09500000 0x0 0x00700000>; /* Runner NAT Cache */
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freq = <800>; /* MHz */
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lag-ports = < 0 1 2 >;
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};
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aon_pin_ctrl: pinmux@f0410700 {
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compatible = "pinctrl-single";
|
|
reg = <0 0xf0410700 0 0xc>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-single,bit-per-mux;
|
|
pinctrl-single,register-width = <32>;
|
|
pinctrl-single,function-mask = <0x1>;
|
|
pinctrl-names = "default";
|
|
};
|
|
|
|
suntop_pmx: pinmux@f0404100 {
|
|
compatible = "pinctrl-single";
|
|
reg = <0 0xf04040a4 0 0xc4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
pinctrl-single,bit-per-mux;
|
|
pinctrl-single,register-width = <32>;
|
|
pinctrl-single,function-mask = <0x1>;
|
|
pinctrl-names = "default";
|
|
};
|
|
|
|
pmb0: pmb@0xd3c03100 {
|
|
compatible = "brcm,pmb";
|
|
reg = <0 0xd3c03100 0 0x50000>;
|
|
#address-cells = <0>;
|
|
#size-cells = <1>;
|
|
direct-access;
|
|
|
|
bpcm@0x7 {
|
|
compatible = "brcm,bpcm";
|
|
reg = <0x7>;
|
|
dev-name = "bpcm-fpm";
|
|
zones = <1>;
|
|
zone-init-pwr = <0x1>;
|
|
dyn-clk-scale-div = <0x1 0x4>;
|
|
};
|
|
|
|
bpcm@0x8 {
|
|
compatible = "brcm,bpcm";
|
|
reg = <0x8>;
|
|
dev-name = "bpcm-cpuc";
|
|
zones = <1>;
|
|
zone-init-pwr = <0x1>;
|
|
};
|
|
|
|
unimac_pwr: bpcm@0xb {
|
|
compatible = "brcm,bpcm";
|
|
reg = <0xb>;
|
|
dev-name = "bpcm-unimac";
|
|
zones = <1>;
|
|
zone-init-pwr = <0x0>;
|
|
dyn-clk-scale-div = <0x1 0x4>;
|
|
};
|
|
};
|
|
|
|
pmb1: pmb@0xf10b0f00 {
|
|
compatible = "brcm,pmb";
|
|
reg = <0 0xf10b0f00 0 0x10>;
|
|
#address-cells = <0>;
|
|
#size-cells = <1>;
|
|
version = <2>;
|
|
|
|
bpcm@0x0 {
|
|
compatible = "brcm,bpcm";
|
|
reg = <0x0>;
|
|
dev-name = "bpcm-rdp";
|
|
zones = <2>;
|
|
zone-init-pwr = <0x3>;
|
|
};
|
|
};
|
|
|
|
i2c_a: i2c@f040a300 {
|
|
clock-frequency = <50000>;
|
|
compatible = "brcm,brcmper-i2c";
|
|
reg = < 0x0 0xf040a300 0x0 0x58>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c_d: i2c@f040a400 {
|
|
clock-frequency = <50000>;
|
|
compatible = "brcm,brcmper-i2c";
|
|
reg = <0x0 0xf040a400 0x0 0x58>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
wbid: wbid@0 {
|
|
compatible = "brcm,wbid";
|
|
reg = <0x24>;
|
|
};
|
|
};
|
|
|
|
ubus-capture {
|
|
compatible = "brcm,ubus-capture";
|
|
reg = < 0x0 0xd3e00000 0x0 0x1000 >,
|
|
< 0x0 0xd7e00000 0x0 0x1000 >;
|
|
segments = < 6 2 >;
|
|
/*
|
|
* There is no reliably timely way to shut off the capture engines.
|
|
* They will shut off eventually after you turn them off, but it
|
|
* takes a while (1 sec?).
|
|
* So we have to filter out our ubus access cycles if we want to
|
|
* capture and display bus errors.
|
|
*/
|
|
// exlude ubus3 engine complex at 0xd3e00000
|
|
address-range = < 0xd3e00000 0xd3e00fff >;
|
|
address-exclude = <1>;
|
|
// exlude ubus3 engine complex at 0xd7e00000
|
|
pid-range = < 95 96 >;
|
|
pid-exclude = <1>;
|
|
enabled-at-boot = "no";
|
|
};
|
|
};
|