forked from Openwrt-EcoNet/openwrt
627daef0cf
Port reset and clock fixes from target/linux/qualcommbe/patches-6.6. Modifications of v6.6 patches are noted in each commit body. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/18796 Signed-off-by: Robert Marko <robimarko@gmail.com>
47 lines
1.5 KiB
Diff
47 lines
1.5 KiB
Diff
From fa691ff57c72a8f0bfeff1a9e86ae2d78765b0da Mon Sep 17 00:00:00 2001
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From: Mantas Pucka <mantas@8devices.com>
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Date: Mon, 31 Mar 2025 15:39:59 +0300
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Subject: [PATCH] clk: qcom: nsscc-ipq9574: fix port5 clock config
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Currently there is no configuration to derive 25/125MHz port5 clock
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from uniphy1 running at 125MHz. This is needed for SGMII mode when
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port5 is using uniphy1.
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Fix this by adding option such clock config option.
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Signed-off-by: Mantas Pucka <mantas@8devices.com>
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---
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drivers/clk/qcom/nsscc-ipq9574.c | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/drivers/clk/qcom/nsscc-ipq9574.c
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+++ b/drivers/clk/qcom/nsscc-ipq9574.c
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@@ -383,11 +383,13 @@ static const struct freq_multi_tbl ftbl_
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static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_25[] = {
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C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0),
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+ C(P_UNIPHY1_NSS_RX_CLK, 5, 0, 0),
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C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
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};
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static const struct freq_conf ftbl_nss_cc_port5_rx_clk_src_125[] = {
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C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0),
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+ C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
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C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
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};
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@@ -408,11 +410,13 @@ static const struct freq_multi_tbl ftbl_
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static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_25[] = {
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C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0),
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+ C(P_UNIPHY1_NSS_TX_CLK, 5, 0, 0),
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C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
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};
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static const struct freq_conf ftbl_nss_cc_port5_tx_clk_src_125[] = {
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C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0),
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+ C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
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C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
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};
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