forked from Openwrt-EcoNet/openwrt
390e516a3b
This driver is cherry-picked from target/linux/qualcommbe/patches-6.6. While Qualcomm did submit past patches for QCA8084, the code has since ben split from at803x. The existing OpenWRT version of the patch is the cleanest version I could find. Add it here. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/18796 Signed-off-by: Robert Marko <robimarko@gmail.com>
86 lines
2.8 KiB
Diff
86 lines
2.8 KiB
Diff
From 5a57611512593212b7fd9c23b4d96486bab6dee3 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Wed, 8 Nov 2023 16:18:02 +0800
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Subject: [PATCH] net: phy: qca808x: Add config_init function for QCA8084
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1. The ADC of QCA8084 PHY must be configured as edge inverted
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and falling whenever it is initialized or reset. In addition,
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the default MSE (Mean square error) threshold value is adjusted,
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which comes into play during link partner detection to detect
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the valid link signal.
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2. Add the possible interface modes.
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When QCA8084 works on the interface mode SGMII or 2500BASE-X, the
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interface mode can be switched according to the PHY link speed.
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When QCA8084 works on the 10G-QXGMII mode, which will be the only
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possible interface mode.
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Change-Id: I832c0d0b069e95cc411a8a7b680a5f60e1d6041a
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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---
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drivers/net/phy/qcom/qca808x.c | 38 ++++++++++++++++++++++++++++++++++
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1 file changed, 38 insertions(+)
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--- a/drivers/net/phy/qcom/qca808x.c
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+++ b/drivers/net/phy/qcom/qca808x.c
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@@ -94,6 +94,15 @@
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#define QCA8084_MMD3_CDT_NEAR_CTRL 0x807f
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#define QCA8084_CDT_NEAR_BYPASS BIT(15)
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+/* QCA8084 ADC clock edge */
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+#define QCA8084_ADC_CLK_SEL 0x8b80
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+#define QCA8084_ADC_CLK_SEL_ACLK GENMASK(7, 4)
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+#define QCA8084_ADC_CLK_SEL_ACLK_FALL 0xf
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+#define QCA8084_ADC_CLK_SEL_ACLK_RISE 0x0
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+
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+#define QCA8084_MSE_THRESHOLD 0x800a
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+#define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6
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+
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MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi, Luo Jie");
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MODULE_LICENSE("GPL");
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@@ -660,6 +669,34 @@ static int qca808x_led_polarity_set(stru
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active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
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}
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+static int qca8084_config_init(struct phy_device *phydev)
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+{
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+ int ret;
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+
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+ if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII)
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+ __set_bit(PHY_INTERFACE_MODE_10G_QXGMII,
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+ phydev->possible_interfaces);
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+ else
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+ qca808x_fill_possible_interfaces(phydev);
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+
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+ /* Configure the ADC to convert the signal using falling edge
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+ * instead of the default rising edge.
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+ */
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+ ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL,
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+ QCA8084_ADC_CLK_SEL_ACLK,
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+ FIELD_PREP(QCA8084_ADC_CLK_SEL_ACLK,
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+ QCA8084_ADC_CLK_SEL_ACLK_FALL));
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+ if (ret < 0)
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+ return ret;
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+
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+ /* Adjust MSE threshold value to avoid link issue with
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+ * some link partner.
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+ */
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+ return phy_write_mmd(phydev, MDIO_MMD_PMAPMD,
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+ QCA8084_MSE_THRESHOLD,
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+ QCA8084_MSE_THRESHOLD_2P5G_VAL);
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+}
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+
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static struct phy_driver qca808x_driver[] = {
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{
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/* Qualcomm QCA8081 */
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@@ -708,6 +745,7 @@ static struct phy_driver qca808x_driver[
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.soft_reset = qca808x_soft_reset,
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.cable_test_start = qca808x_cable_test_start,
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.cable_test_get_status = qca808x_cable_test_get_status,
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+ .config_init = qca8084_config_init,
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}, };
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module_phy_driver(qca808x_driver);
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