forked from Openwrt-EcoNet/openwrt
01f3624960
Add dts fixes from linux-next. Two patches from the NSSCC series are still in -next did not yet land in mainline, as well as misc other DTS changes. Add them here. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/18796 Signed-off-by: Robert Marko <robimarko@gmail.com>
69 lines
1.6 KiB
Diff
69 lines
1.6 KiB
Diff
From a7c88bc81632974c0708308493aefb1f871b65fa Mon Sep 17 00:00:00 2001
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From: Md Sadre Alam <quic_mdalam@quicinc.com>
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Date: Thu, 6 Mar 2025 17:03:56 +0530
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Subject: [PATCH] arm64: dts: qcom: ipq9574: Enable SPI NAND for ipq9574
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Enable SPI NAND support for ipq9574 SoC.
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Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
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Link: https://lore.kernel.org/r/20250306113357.126602-3-quic_mdalam@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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.../boot/dts/qcom/ipq9574-rdp-common.dtsi | 44 +++++++++++++++++++
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1 file changed, 44 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp-common.dtsi
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@@ -146,6 +146,50 @@
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drive-strength = <8>;
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bias-pull-up;
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};
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+
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+ qpic_snand_default_state: qpic-snand-default-state {
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+ clock-pins {
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+ pins = "gpio5";
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+ function = "qspi_clk";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+
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+ cs-pins {
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+ pins = "gpio4";
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+ function = "qspi_cs";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+
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+ data-pins {
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+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
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+ function = "qspi_data";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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+};
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+
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+&qpic_bam {
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+ status = "okay";
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+};
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+
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+&qpic_nand {
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+ pinctrl-0 = <&qpic_snand_default_state>;
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+ pinctrl-names = "default";
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+
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+ status = "okay";
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+
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+ flash@0 {
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+ compatible = "spi-nand";
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+ reg = <0>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ nand-ecc-engine = <&qpic_nand>;
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+ nand-ecc-strength = <4>;
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+ nand-ecc-step-size = <512>;
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+ };
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};
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&usb_0_dwc3 {
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