forked from Openwrt-EcoNet/openwrt
ebfd69a3e3
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.12.32 All patches are automatically refreshed. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Tested-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/19027 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
55 lines
1.5 KiB
Diff
55 lines
1.5 KiB
Diff
From 52ebd52aa1906961142a2aba55d47a53b956847c Mon Sep 17 00:00:00 2001
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From: Devi Priya <quic_devipriy@quicinc.com>
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Date: Thu, 13 Mar 2025 16:33:58 +0530
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Subject: [PATCH] arm64: dts: qcom: ipq9574: Add nsscc node
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Add a node for the nss clock controller found on ipq9574 based devices.
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Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
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Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
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Link: https://lore.kernel.org/r/20250313110359.242491-6-quic_mmanikan@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq9574.dtsi | 29 +++++++++++++++++++++++++++
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1 file changed, 29 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
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@@ -1195,6 +1195,35 @@
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status = "disabled";
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};
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+ nsscc: clock-controller@39b00000 {
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+ compatible = "qcom,ipq9574-nsscc";
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+ reg = <0x39b00000 0x80000>;
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+ clocks = <&xo_board_clk>,
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+ <&cmn_pll NSS_1200MHZ_CLK>,
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+ <&cmn_pll PPE_353MHZ_CLK>,
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+ <&gcc GPLL0_OUT_AUX>,
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+ <0>,
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+ <0>,
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+ <0>,
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+ <0>,
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+ <0>,
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+ <0>,
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+ <&gcc GCC_NSSCC_CLK>;
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+ clock-names = "xo",
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+ "nss_1200",
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+ "ppe_353",
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+ "gpll0_out",
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+ "uniphy0_rx",
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+ "uniphy0_tx",
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+ "uniphy1_rx",
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+ "uniphy1_tx",
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+ "uniphy2_rx",
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+ "uniphy2_tx",
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+ "bus";
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ #interconnect-cells = <1>;
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+ };
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};
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thermal-zones {
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