forked from Openwrt-EcoNet/openwrt
e3478dbd69
Add relevant patches from upstream, up to v5.16-rc6. The gaps in the patch numbersing are either patches that were picked into the stable kernel (6.12.y), or that are already backported in target/linux/generic. The gaps makes it easy for me to pick these patches from my working kernel git branch. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/18796 Signed-off-by: Robert Marko <robimarko@gmail.com>
106 lines
2.8 KiB
Diff
106 lines
2.8 KiB
Diff
From 66fde1c5d29006127cc4fc5a12a0c42415c098bd Mon Sep 17 00:00:00 2001
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From: Md Sadre Alam <quic_mdalam@quicinc.com>
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Date: Mon, 24 Feb 2025 16:44:13 +0530
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Subject: [PATCH 16/22] v6.15: spi: dt-bindings: Introduce qcom,spi-qpic-snand
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Document the QPIC-SPI-NAND flash controller present in the IPQ SoCs.
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It can work both in serial and parallel mode and supports typical
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SPI-NAND page cache operations.
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
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Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
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Link: https://patch.msgid.link/20250224111414.2809669-2-quic_mdalam@quicinc.com
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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.../bindings/spi/qcom,spi-qpic-snand.yaml | 83 +++++++++++++++++++
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1 file changed, 83 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qpic-snand.yaml
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@@ -0,0 +1,83 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/spi/qcom,spi-qpic-snand.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Qualcomm QPIC NAND controller
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+
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+maintainers:
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+ - Md sadre Alam <quic_mdalam@quicinc.com>
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+
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+description:
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+ The QCOM QPIC-SPI-NAND flash controller is an extended version of
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+ the QCOM QPIC NAND flash controller. It can work both in serial
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+ and parallel mode. It supports typical SPI-NAND page cache
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+ operations in single, dual or quad IO mode with pipelined ECC
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+ encoding/decoding using the QPIC ECC HW engine.
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+
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+allOf:
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+ - $ref: /schemas/spi/spi-controller.yaml#
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+
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+properties:
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+ compatible:
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+ enum:
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+ - qcom,ipq9574-snand
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+
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+ reg:
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+ maxItems: 1
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+
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+ clocks:
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+ maxItems: 3
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+
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+ clock-names:
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+ items:
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+ - const: core
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+ - const: aon
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+ - const: iom
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+
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+ dmas:
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+ items:
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+ - description: tx DMA channel
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+ - description: rx DMA channel
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+ - description: cmd DMA channel
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+
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+ dma-names:
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+ items:
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+ - const: tx
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+ - const: rx
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+ - const: cmd
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - clock-names
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+
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+unevaluatedProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
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+ spi@79b0000 {
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+ compatible = "qcom,ipq9574-snand";
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+ reg = <0x1ac00000 0x800>;
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+
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+ clocks = <&gcc GCC_QPIC_CLK>,
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+ <&gcc GCC_QPIC_AHB_CLK>,
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+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
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+ clock-names = "core", "aon", "iom";
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ flash@0 {
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+ compatible = "spi-nand";
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+ reg = <0>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ nand-ecc-engine = <&qpic_nand>;
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+ nand-ecc-strength = <4>;
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+ nand-ecc-step-size = <512>;
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+ };
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+ };
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