forked from Openwrt-EcoNet/openwrt
e3478dbd69
Add relevant patches from upstream, up to v5.16-rc6. The gaps in the patch numbersing are either patches that were picked into the stable kernel (6.12.y), or that are already backported in target/linux/generic. The gaps makes it easy for me to pick these patches from my working kernel git branch. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/18796 Signed-off-by: Robert Marko <robimarko@gmail.com>
153 lines
3.0 KiB
Diff
153 lines
3.0 KiB
Diff
From 695cb0b8f9c525fe6d3ffbc349bc6087acd71201 Mon Sep 17 00:00:00 2001
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From: devi priya <quic_devipriy@quicinc.com>
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Date: Thu, 1 Aug 2024 11:18:02 +0530
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Subject: [PATCH 05/22] v6.14: arm64: dts: qcom: ipq9574: Enable PCIe PHYs and
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controllers
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Enable the PCIe controller and PHY nodes corresponding to RDP 433.
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Signed-off-by: devi priya <quic_devipriy@quicinc.com>
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Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
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Link: https://lore.kernel.org/r/20240801054803.3015572-4-quic_srichara@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts | 113 ++++++++++++++++++++
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1 file changed, 113 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
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+++ b/arch/arm64/boot/dts/qcom/ipq9574-rdp433.dts
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@@ -8,6 +8,7 @@
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/dts-v1/;
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+#include <dt-bindings/gpio/gpio.h>
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#include "ipq9574-rdp-common.dtsi"
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/ {
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@@ -15,6 +16,45 @@
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compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
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};
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+&pcie1_phy {
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+ status = "okay";
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+};
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+
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+&pcie1 {
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+ pinctrl-0 = <&pcie1_default>;
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+ pinctrl-names = "default";
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+
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+ perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
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+ wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
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+ status = "okay";
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+};
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+
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+&pcie2_phy {
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+ status = "okay";
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+};
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+
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+&pcie2 {
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+ pinctrl-0 = <&pcie2_default>;
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+ pinctrl-names = "default";
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+
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+ perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
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+ wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
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+ status = "okay";
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+};
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+
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+&pcie3_phy {
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+ status = "okay";
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+};
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+
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+&pcie3 {
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+ pinctrl-0 = <&pcie3_default>;
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+ pinctrl-names = "default";
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+
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+ perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
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+ wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
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+ status = "okay";
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+};
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+
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&sdhc_1 {
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pinctrl-0 = <&sdc_default_state>;
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pinctrl-names = "default";
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@@ -28,6 +68,79 @@
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};
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&tlmm {
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+
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+ pcie1_default: pcie1-default-state {
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+ clkreq-n-pins {
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+ pins = "gpio25";
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+ function = "pcie1_clk";
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+ drive-strength = <6>;
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+ bias-pull-up;
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+ };
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+
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+ perst-n-pins {
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+ pins = "gpio26";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ output-low;
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+ };
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+
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+ wake-n-pins {
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+ pins = "gpio27";
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+ function = "pcie1_wake";
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+ drive-strength = <6>;
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+ bias-pull-up;
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+ };
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+ };
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+
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+ pcie2_default: pcie2-default-state {
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+ clkreq-n-pins {
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+ pins = "gpio28";
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+ function = "pcie2_clk";
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+ drive-strength = <6>;
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+ bias-pull-up;
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+ };
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+
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+ perst-n-pins {
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+ pins = "gpio29";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ output-low;
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+ };
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+
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+ wake-n-pins {
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+ pins = "gpio30";
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+ function = "pcie2_wake";
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+ drive-strength = <6>;
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+ bias-pull-up;
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+ };
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+ };
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+
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+ pcie3_default: pcie3-default-state {
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+ clkreq-n-pins {
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+ pins = "gpio31";
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+ function = "pcie3_clk";
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+ drive-strength = <6>;
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+ bias-pull-up;
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+ };
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+
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+ perst-n-pins {
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+ pins = "gpio32";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ output-low;
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+ };
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+
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+ wake-n-pins {
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+ pins = "gpio33";
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+ function = "pcie3_wake";
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+ drive-strength = <6>;
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+ bias-pull-up;
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+ };
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+ };
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+
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sdc_default_state: sdc-default-state {
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clk-pins {
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pins = "gpio5";
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