forked from Openwrt-EcoNet/openwrt
da2c83327f
Use latest patches sent upstream for review for IPQ5018 GE PHY support: - Move enablement of the LDO controller to the mdio-ipq4019 driver away from the CMN PLL driver - Remove the different patches to add CDT, MSE, AZ, and DAC support they are all contained in the upstreamed driver. Accordingly, also set the right property in the DTS for Linksys SPNMX56 to set the right DAC values to accommodate for the short cable length. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/18774 Signed-off-by: Robert Marko <robimarko@gmail.com>
83 lines
2.3 KiB
Diff
83 lines
2.3 KiB
Diff
From 1b733e878ac1292c6e0f2e9a49685b80c35619b0 Mon Sep 17 00:00:00 2001
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Mon, 02 Jun 2025 12:50:41 +0400
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Subject: [PATCH v3 5/5] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus
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MIME-Version: 1.0
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Content-Type: text/plain; charset="utf-8"
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Content-Transfer-Encoding: 7bit
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Message-Id: <20250602-ipq5018-ge-phy-v3-5-0d8f39f402a6@outlook.com>
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The IPQ5018 SoC contains an internal GE PHY, always at phy address 7.
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As such, let's add the GE PHY node to the SoC dtsi.
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The LDO controller found in the SoC must be enabled to provide constant
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low voltages to the PHY. The mdio-ipq4019 driver already has support
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for this, so adding the appropriate TCSR register offset.
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In addition, the GE PHY outputs both the RX and TX clocks to the GCC
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which gate controls them and routes them back to the PHY itself.
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So let's create two DT fixed clocks and register them in the GCC node.
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Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 26 +++++++++++++++++++++++---
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1 file changed, 23 insertions(+), 3 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -22,6 +22,18 @@
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#clock-cells = <0>;
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};
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+ gephy_rx_clk: gephy-rx-clk {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ #clock-cells = <0>;
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+ };
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+
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+ gephy_tx_clk: gephy-tx-clk {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ #clock-cells = <0>;
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+ };
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+
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -190,7 +202,8 @@
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mdio0: mdio@88000 {
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compatible = "qcom,ipq5018-mdio";
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- reg = <0x00088000 0x64>;
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+ reg = <0x00088000 0x64>,
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+ <0x019475c4 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -198,6 +211,13 @@
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clock-names = "gcc_mdio_ahb_clk";
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status = "disabled";
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+
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+ ge_phy: ethernet-phy@7 {
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+ compatible = "ethernet-phy-id004d.d0c0";
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+ reg = <7>;
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+
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+ resets = <&gcc GCC_GEPHY_MISC_ARES>;
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+ };
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};
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mdio1: mdio@90000 {
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@@ -392,8 +412,8 @@
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<&pcie0_phy>,
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<&pcie1_phy>,
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<0>,
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- <0>,
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- <0>,
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+ <&gephy_rx_clk>,
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+ <&gephy_tx_clk>,
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<0>,
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<0>;
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#clock-cells = <1>;
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