forked from Openwrt-EcoNet/openwrt
da2c83327f
Use latest patches sent upstream for review for IPQ5018 GE PHY support: - Move enablement of the LDO controller to the mdio-ipq4019 driver away from the CMN PLL driver - Remove the different patches to add CDT, MSE, AZ, and DAC support they are all contained in the upstreamed driver. Accordingly, also set the right property in the DTS for Linksys SPNMX56 to set the right DAC values to accommodate for the short cable length. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/18774 Signed-off-by: Robert Marko <robimarko@gmail.com>
56 lines
1.6 KiB
Diff
56 lines
1.6 KiB
Diff
From 97a159dd7747724619e54cb3460d9b8d4ed08be7 Mon Sep 17 00:00:00 2001
|
|
From: George Moussalem <george.moussalem@outlook.com>
|
|
Date: Mon, 02 Jun 2025 12:50:40 +0400
|
|
Subject: [PATCH v3 4/5] arm64: dts: qcom: ipq5018: Add MDIO buses
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset="utf-8"
|
|
Content-Transfer-Encoding: 7bit
|
|
Message-Id: <20250602-ipq5018-ge-phy-v3-4-0d8f39f402a6@outlook.com>
|
|
|
|
IPQ5018 contains two mdio buses of which one bus is used to control the
|
|
SoC's internal GE PHY, while the other bus is connected to external PHYs
|
|
or switches.
|
|
|
|
There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's
|
|
simply add the mdio nodes for them.
|
|
|
|
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
|
|
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|
---
|
|
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++
|
|
1 file changed, 24 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
|
@@ -188,6 +188,30 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ mdio0: mdio@88000 {
|
|
+ compatible = "qcom,ipq5018-mdio";
|
|
+ reg = <0x00088000 0x64>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ clocks = <&gcc GCC_MDIO0_AHB_CLK>;
|
|
+ clock-names = "gcc_mdio_ahb_clk";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ mdio1: mdio@90000 {
|
|
+ compatible = "qcom,ipq5018-mdio";
|
|
+ reg = <0x00090000 0x64>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+
|
|
+ clocks = <&gcc GCC_MDIO1_AHB_CLK>;
|
|
+ clock-names = "gcc_mdio_ahb_clk";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
cmn_pll: clock-controller@9b000 {
|
|
compatible = "qcom,ipq9574-cmn-pll";
|
|
reg = <0x0009b000 0x800>;
|