forked from Openwrt-EcoNet/openwrt
Use latest patches sent upstream for review for IPQ5018 GE PHY support: - Move enablement of the LDO controller to the mdio-ipq4019 driver away from the CMN PLL driver - Remove the different patches to add CDT, MSE, AZ, and DAC support they are all contained in the upstreamed driver. Accordingly, also set the right property in the DTS for Linksys SPNMX56 to set the right DAC values to accommodate for the short cable length. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/18774 Signed-off-by: Robert Marko <robimarko@gmail.com>
33 lines
1.3 KiB
Diff
33 lines
1.3 KiB
Diff
From 19600588e6403ff9f6c1e985fc025afb9160a56f Mon Sep 17 00:00:00 2001
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Wed, 28 May 2025 08:37:25 +0400
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Subject: [PATCH v2 2/5] clk: qcom: gcc-ipq5018: fix GE PHY reset
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MIME-Version: 1.0
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Content-Type: text/plain; charset="utf-8"
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Content-Transfer-Encoding: 7bit
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Message-Id: <20250528-ipq5018-ge-phy-v2-2-68fc3a8248dd@outlook.com>
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The MISC reset is supposed to trigger a resets across the MDC, DSP, and
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RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask
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of the reset definition accordingly in the GCC as per the downstream
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driver.
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Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/00743c3e82fa87cba4460e7a2ba32f473a9ce932
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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---
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drivers/clk/qcom/gcc-ipq5018.c | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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--- a/drivers/clk/qcom/gcc-ipq5018.c
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+++ b/drivers/clk/qcom/gcc-ipq5018.c
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@@ -3660,7 +3660,7 @@ static const struct qcom_reset_map gcc_i
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[GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },
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[GCC_WCSS_Q6_BCR] = { 0x18004, 0 },
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[GCC_WCSSAON_RESET] = { 0x59010, 0},
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- [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },
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+ [GCC_GEPHY_MISC_ARES] = { 0x56004, .bitmask = GENMASK(3, 0) },
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};
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static const struct of_device_id gcc_ipq5018_match_table[] = {
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