forked from Openwrt-EcoNet/openwrt
08ff2807cf
Use upstreamed patches for IPQ5018 PCIe support, including patches for phy and controller drivers and dts nodes. Signed-off-by: George Moussalem <george.moussalem@outlook.com> Link: https://github.com/openwrt/openwrt/pull/18884 Signed-off-by: Robert Marko <robimarko@gmail.com>
87 lines
2.5 KiB
Diff
87 lines
2.5 KiB
Diff
From dfc820d2f8a8ea90bbc02269b5362e3678e58cac Mon Sep 17 00:00:00 2001
|
|
From: Nitheesh Sekar <quic_nsekar@quicinc.com>
|
|
Date: Wed, 26 Mar 2025 12:10:56 +0400
|
|
Subject: [PATCH] phy: qualcomm: qcom-uniphy-pcie 28LP add support for IPQ5018
|
|
|
|
The Qualcomm UNIPHY PCIe PHY 28LP is found on both IPQ5332 and IPQ5018.
|
|
Adding the PHY init sequence, pipe clock rate, and compatible for IPQ5018.
|
|
|
|
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
|
|
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
|
|
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
|
|
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|
Link: https://lore.kernel.org/r/20250326-ipq5018-pcie-v7-2-e1828fef06c9@outlook.com
|
|
Signed-off-by: Vinod Koul <vkoul@kernel.org>
|
|
---
|
|
.../phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c | 45 +++++++++++++++++++
|
|
1 file changed, 45 insertions(+)
|
|
|
|
--- a/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
|
|
+++ b/drivers/phy/qualcomm/phy-qcom-uniphy-pcie-28lp.c
|
|
@@ -75,6 +75,40 @@ struct qcom_uniphy_pcie {
|
|
|
|
#define phy_to_dw_phy(x) container_of((x), struct qca_uni_pcie_phy, phy)
|
|
|
|
+static const struct qcom_uniphy_pcie_regs ipq5018_regs[] = {
|
|
+ {
|
|
+ .offset = SSCG_CTRL_REG_4,
|
|
+ .val = 0x1cb9,
|
|
+ }, {
|
|
+ .offset = SSCG_CTRL_REG_5,
|
|
+ .val = 0x023a,
|
|
+ }, {
|
|
+ .offset = SSCG_CTRL_REG_3,
|
|
+ .val = 0xd360,
|
|
+ }, {
|
|
+ .offset = SSCG_CTRL_REG_1,
|
|
+ .val = 0x1,
|
|
+ }, {
|
|
+ .offset = SSCG_CTRL_REG_2,
|
|
+ .val = 0xeb,
|
|
+ }, {
|
|
+ .offset = CDR_CTRL_REG_4,
|
|
+ .val = 0x3f9,
|
|
+ }, {
|
|
+ .offset = CDR_CTRL_REG_5,
|
|
+ .val = 0x1c9,
|
|
+ }, {
|
|
+ .offset = CDR_CTRL_REG_2,
|
|
+ .val = 0x419,
|
|
+ }, {
|
|
+ .offset = CDR_CTRL_REG_1,
|
|
+ .val = 0x200,
|
|
+ }, {
|
|
+ .offset = PCS_INTERNAL_CONTROL_2,
|
|
+ .val = 0xf101,
|
|
+ },
|
|
+};
|
|
+
|
|
static const struct qcom_uniphy_pcie_regs ipq5332_regs[] = {
|
|
{
|
|
.offset = PHY_CFG_PLLCFG,
|
|
@@ -88,6 +122,14 @@ static const struct qcom_uniphy_pcie_reg
|
|
},
|
|
};
|
|
|
|
+static const struct qcom_uniphy_pcie_data ipq5018_data = {
|
|
+ .lane_offset = 0x800,
|
|
+ .phy_type = PHY_TYPE_PCIE_GEN2,
|
|
+ .init_seq = ipq5018_regs,
|
|
+ .init_seq_num = ARRAY_SIZE(ipq5018_regs),
|
|
+ .pipe_clk_rate = 125 * MEGA,
|
|
+};
|
|
+
|
|
static const struct qcom_uniphy_pcie_data ipq5332_data = {
|
|
.lane_offset = 0x800,
|
|
.phy_type = PHY_TYPE_PCIE_GEN3,
|
|
@@ -212,6 +254,9 @@ static inline int phy_pipe_clk_register(
|
|
|
|
static const struct of_device_id qcom_uniphy_pcie_id_table[] = {
|
|
{
|
|
+ .compatible = "qcom,ipq5018-uniphy-pcie-phy",
|
|
+ .data = &ipq5018_data,
|
|
+ }, {
|
|
.compatible = "qcom,ipq5332-uniphy-pcie-phy",
|
|
.data = &ipq5332_data,
|
|
}, {
|